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We present the design and the performance of a hierarchical associative memory (AM) based on phase locking of coupled oscillators used for pattern recognition. The use of coupled oscillators, rather than Boolean logic, provides for implementations using emerging nanotechnology, such as magnetic spin-torque oscillators and resonant body transistor oscillators, which have the potential of lower energy and higher density than CMOS solutions. We develop a model for the general behavior of weakly coupled nonlinear oscillators that perform pattern matching using a simulation of coupled CMOS ring oscillators. We derive a simple analytic model for their phase locking behavior and use this reduced model in a hierarchical AM for image recognition tasks, such as identifying handwritten numbers.

The operation of an array of coupled oscillators underlying the associative memory function is demonstrated for various interconnection topologies (cross-connect and star-coupled). Three types of nonlinear oscillators (Andronov-Hopf, phase-locked loop, and spin torque) and their synchronization behavior are compared. Frequency-shift keying scheme of encoding input and memorized data is introduced. The speed of synchronization of oscillators and the evolution of the degree of match are studied as a function of device parameters.

A new method that uses statistical distribution of prediction error vectors to build models of time series patterns has been developed. A universal predictor is firstly established from universal training data. Then, properties common to all the patterns are removed from the training data by the predictor. The residuals, i.e., the prediction errors, hold the characteristics of individual patterns. After clustering the prediction errors to a universal codebook, the predictor and the codebook are applied to individual training data sets to obtain the usage histograms of code vectors in the universal codebook, namely, the statistical distribution of prediction error vectors. These histograms represent the properties of individual patterns, and can be used as models in pattern recognition applications. This method is not restricted to any specific signals. As a demonstration, we utilized it to speaker identification application. It performed as well as other modeling methods under the text-dependent condition.

We present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.