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Aim To study the epidemiology and clinical outcomes of catheter-related infections of Serratia species in peritoneal dialysis (PD) patients. Methods We retrospectively reviewed the patient characteristics, antibiotics susceptibility/resistance patterns and treatment outcomes of exit site infection (ESI) and peritonitis due to Serratia in PD patients during the period of 2004 to 2017. Results One hundred and sixty-one patients had Serratia ESI, of which 10 (6.2%) progressed to tunnel tract involvement and 11 (6.8%) developed PD peritonitis. Nineteen (11.8%) patients with Serratia ESI failed to respond to medical treatment and required catheter removal. Fifty-six (34.8%) patients had repeat Serratia ESI, which occurred at 12.9 ± 13.6 months after the previous episode. Twenty-two patients had Serratia peritonitis, which accounted for 1% of peritonitis during the study period. Ten (45.5%) patients responded to medical treatment while 12 (54.5%) patients required catheter removal. Nine patients (36.4%) failed to resume PD and were converted to long-term haemodialysis. Two patients had repeat peritonitis at 2 months and 3 years, respectively, after the initial episode. Serratia species in PD patients showed high rates of resistance to ampicillin, and first- and second-generation cephalosporins, but were generally susceptible to aminoglycosides, carboxy-/ureido-penicillins and carbapenems. Conclusion Our results suggest that Serratia ESI show low risk of progression to peritonitis and favourable response to medical therapy, while Serratia peritonitis was associated with high rates of catheter removal and peritoneal failure.

Noise complaints in restaurants have been accelerating and unpleasant sounds erode customer satisfaction. Restaurant ambient noise, such as background and physical sounds influence customer satisfaction and effectively controlling the sound environment in restaurants is challenging, particularly situational sounds generated by customers. Situational sounds address how customers are influenced by other customers dining in the same restaurant and highlight a type of sound that cannot be easily managed by employees. Situational sounds can be loud conversation among fellow customers or misbehaving children. Concerns with situational sounds are less about how they impact customer satisfaction, and more about the way in which managers handle them. Thus, managers find a proactive service approach to be most effective when handling situational sounds in a restaurant. For example, strategically placing a large noisy group in a separate room or further away from other customers in the restaurant can mitigate the negative impact to other diners. The results of this study confirmed that background sounds, physical sounds, and managers’ proactive customer service regarding situational sounds impact customer satisfaction. However, the interactive effects of background sounds, physical sounds, and managers’ proactive customer service regarding situational sounds do not influence customer satisfaction. Based on the results, recommendations for restaurant managers are provided to decrease controllable unpleasant noises caused by background and physical sounds as well as strategies for effectively executing proactive customer service to handle situational sounds.

Objective:\ud \ud Fruit and vegetable (F&V) consumption is of central importance to many diet-related health outcomes. In India, caste is a major basis of socioeconomic inequality. Recent analysis shows that more disadvantaged “lower” castes consume less F&V than the rest. This article explores whether this consumption gap arises due to differential distribution of drivers of consumption such as income and education across castes, or whether behavioral differences or discrimination may be at play.\ud \ud \ud Design:\ud \ud The Oaxaca-Blinder regression decomposition is applied to explain the gap in F&V consumption between “upper” castes and “lower” castes, using data from the 68th (2011-2012) round of the National Sample Survey Organization household survey.\ud \ud \ud Results:\ud \ud Differences in the distribution of F&V drivers account for all of the 50 grams/person/day consumption gap between upper and lower castes. In particular, much of the gap is explained by income differential across castes.\ud \ud \ud Conclusions:\ud \ud In the long run, India’s positive discrimination policies in education and employment that seek to equalize income across castes are also likely to help close the F&V consumption gap, leading to health benefits. In the medium run, interventions acting to boost lower caste income, such as cash transfers targeting lower castes, may be effective.

This article presents a Built-in self-test (BIST) solution for polar transceivers with low cost and high accuracy. Radio frequency (RF) Polar transceivers are desirable for portable devices due to higher power efficiency compared to traditional RF Cartesian transceivers. Unfortunately, their design is quite challenging due to substantially different signal paths that need to work coherently to ensure signal quality. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude. In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion, which leads to violation of spectral mask requirements. Typically, these parameters are not directly measured but calibrated through spectral analysis using expensive RF equipment, leading to lengthy and costly measurement/calibration cycles. However, characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. In this article, we propose a technique to measure with the intent to calibrate impairments of the polar transceiver in the loop-back mode. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments accurately.

We investigate the impact of the new LUNA rate for the nuclear reaction $^{22}$Ne$(p,\gamma)^{23}$Na on the chemical ejecta of intermediate-mass stars, with particular focus on the thermally-pulsing asymptotic giant branch (TP-AGB) stars that experience hot-bottom burning. To this aim we use the PARSEC and COLIBRI codes to compute the complete evolution, from the pre-main sequence up to the termination of the TP-AGB phase, of a set of stellar models with initial masses in the range $3.0\,M_{\odot} - 6.0\,M_{\odot}$, and metallicities $Z_{\rm i}=0.0005$, $Z_{\rm i}=0.006$, and $Z_{\rm i} = 0.014$. We find that the new LUNA measures have much reduced the nuclear uncertainties of the $^{22}$Ne and $^{23}$Na AGB ejecta, which drop from factors of $\simeq 10$ to only a factor of few for the lowest metallicity models. Relying on the most recent estimations for the destruction rate of $^{23}$Na, the uncertainties that still affect the $^{22}$Ne and $^{23}$Na AGB ejecta are mainly dominated by evolutionary aspects (efficiency of mass-loss, third dredge-up, convection). Finally, we discuss how the LUNA results impact on the hypothesis that invokes massive AGB stars as the main agents of the observed O-Na anti-correlation in Galactic globular clusters. We derive quantitative indications on the efficiencies of key physical processes (mass loss, third dredge-up, sodium destruction) in order to simultaneously reproduce both the Na-rich, O-poor extreme of the anti-correlation, and the observational constraints on the CNO abundance. Results for the corresponding chemical ejecta are made publicly available., Comment: 21 pages, 14 figures, accepted for publication in MNRAS

In this paper, we show that clock faults producing duty-cycle variations, which have been proven very likely, can give rise to min or max delay violations. This mandates new, specific testing approaches for clock faults, to avoid them to compromise the system correct operation in the field, with dramatic effects on product quality and defect level. We then introduce a new scheme that can be employed to detect the clock faults causing duty-cycle variations.

Care transition, the process of moving from community care to residential care, is one of the biggest changes that older people can experience in their later life. Evidence from the literature suggests that older people's experiences of care transition tend to be negative and traumatic, with most of them being little involved in the process of care transition. How older people exercise choice during the period of care transition is important for understanding their experiences of care transition for the following two reasons: first, choice has been referred to in the literature as the key to less stressful care transition experiences, which can subsequently lead to a better quality of life in residential homes; second, the introduction of choice in public services has been the key plank of British social policy in recent decades and there has been a movement towards extending choice in residential care. This research aims to study older people's care transition experiences and their exercise of choice during the process of care transition, to explore the meaning and the perceived effects of choice and to identify the role of choice in promoting a positive care transition. This thesis presents findings from 48 in-depth interviews with older people who became new residents in one of the ten participating residential homes in London and had their care paid for by the local authority. This research identified four groups of older people who showed marked differences in terms of their needs, their exercise of choice during the care transition process and their adaptation to residential care: Active Planners, Conformists, the Unsettled and Shelter-Seekers. The findings from this research suggest that the older people's care transition experiences varied and that they stretch beyond the prevailing evidence emphasising the stressfulness of the care transition. The cases of Active Planners and Shelter-Seekers show the potential for positive roles for care homes in the case of users with genuine needs for residential care. An overwhelming majority of the older people who were interviewed were great proponents of choice and many of them actively exercised choice in the course of their care transition. This challenges the claim of the passivity of older people which has been argued in the literature. However, the cases of some Conformists who did not want to exercise choice also highlight that having no choice can be a choice for some older people. On the whole, older people’s exercise of choice played an important role in facilitating a positive transition, despite it not being a precondition for such a transition. However, there were administrative issues limiting the level and the extent of choice that were available to the older people and the Unsettled experienced an undesired move into a care home, having their choices denied or rejected. This thesis also questions the working of choice and competition in residential care, as the older people did not seem to enjoy the expected benefits of choice relating to service improvements which have been argued for in the literature.

We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated with three-dimensional (3-D) integration technology. In contrast to prior work, we consider the pre-bond test-pin-count constraint during optimization since these pins occupy large silicon area that cannot be used in functional mode. In addition, the proposed test-architecture design takes the SoC layout into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for test-access mechanisms. In addition, a thermal-aware test scheduling algorithm is proposed to eliminate hot spots during manufacturing test. Experimental results for the ITC'02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution.

We propose a low cost scheme for the dynamic compensation in the field of undesired skew and duty cycle variations of local clocks of high performance microprocessors and high end ASICs. Compared to alternate approaches, our solution features lower power consumption, smaller compensation error, and a lower or comparable area overhead.

In this paper we present a low cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in-situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing Ring Oscillators (ROs) to measure process parameter variations, our jitter measurement scheme can be implemented by re-using part of such ROs, thus allowing to measure clock jitter with very limited cost increase compared to process parameter variation measurement only, and with no impact on parameter variation measurement resolution.

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements

As device manufacturers scale their silicon technology, and processor speeds rise above 1 GHz, it's becoming common for every processor company to tout gigahertz processors. To continually improve system-level performance, system designers have begun increasing I/O performance. Some of these changes are evolutionary; some are revolutionary. The latter necessitate a change in test methodology and in the subsequent DFT. Intel's changing its processors' front-side bus from common-clock to source-synchronous (SS) signaling and increasing their bus transfer rate from less than 100 MHz to 800 megatransfers/second (1 MT/s= 1 Mbyte/s/pin). On the chipset side, Intel has upgraded its universal serial bus from 48 Mbps to 400 Mbps and has transitioned to the serial advanced technology attachment (SATA) standard at a 1.25-Gbps data rate. we show how we've solved the testing problem of the SS interface and how this self-test scheme is extendable to other high-speed I/O circuits, including high-speed serial (HSS) signaling.

Silicon Interposer is the new PCB where silicon of different process technologies (like logic, DRAM, analog, etc.) can be bonded onto and integrated into the same package. Silicon interposer has microbumps on one side and flipchip (C4) bumps on the other, and signal on one side are connected to the other with TSV (Through Silicon Vias). Die to die interconnects are just wires from one microbump to another without connecting to any C4 on the bottom side. Essentially, these are tiny PCBs that have their dimensions shrink by 100x. Conceptually PCB essentially are just interconnects so testing really are just open/short and maybe leakage, i.e., ONLY if you can connect (or probe) to the microbumps. However, at 40–50um pitch, they are almost half the pitch of the most advanced flipchip bump technology with tens of thousands of microbumps in a typical application. The tight pitch and mass quantity of microbumps would drive for new probe technologies (read, more expensive) and complex test optimization at the ATE side. There is also no transistors (nor diodes) on this new PCB, so all you learnt about DFT is out the window. At the same time, it is expected to have zero test cost (as yield should be high). Some in the industry have suggested “Pretty Good Interposer”, only testing for systematics and not defects. Is, “pretty good”, good enough to stand in for “known good”? It all depends on what you put on these interposers and potentially yield loss can kill a product's viability. This talk will try to elaborate the challenges and will try to propose new test methods for testing these new, miniature PCB.

Test vehicles are commonly used to understand the characteristics of a new process node. The ability to precisely identify and isolate defects is a key requirement during yield learning on these vehicles. Efficiently utilizing the fanouts in a design is critical to get a smaller pfa area. In this talk, we introduce the concept High Observability Patterns. High observability patterns target the detection of a defect in multiple patterns using multiple and different observe points. This allows the diagnostics engine to more precisely identify where the defect is and thus reducing the PFA area.