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We have fabricated NiGe/Ge diodes and Ge pMISFETs with the NiGe S/D, and studied the electrical characteristics in detail. The NiGe/n-Ge Schottcky S/D is shown to be suitable for Ge pMISFETs. The high performance Ge pMISFETs with sub-100nm gate length has been demonstrated. The dependencies of the inversion layer hole mobility of Ge on the impurity concentration and temperature, and the characteristics of short channel pMISFETs were experimentally examined.

A novel fabrication process and electrical characteristics of uniaxially strained Si and SiGe wire-channel transistors are presented. The uniaxial stress was introduced into the wire channels by anisotropic relaxation of biaxially strained SOI (SSOI) and SGOI (SiGe-on-insulator) substrates. Ge-condensation and hydrogen thermal etching techniques were also employed. The fabricated SSOI-wire n- and SGOI-wire p-MOSFETs exhibited mobility enhancements against both (100)Si surface and control SOI-wire devices due to the uniaxial strain.

An effective wet cleaning process, optimized for low temperature Ge epitaxy on thin Ge or SiGe structures with reduced surface roughening, is proposed. It is found that the HF+HCl cleaning is the most effective wet cleaning method that is applicable to the low temperature thermal cleaning. It is also found that temperature of the thermal cleaning appropriate for thin Germanium on Insulator (GOI) substrates is approximately 450oC. Moreover, the successful formation of the strained-GOI structures is demonstrated by applying these wet and thermal cleaning processes to thin Silicon-Germanium on Insulator (SGOI) substrates.

Recent developments in the Ge condensation technique for the fabrication of the SiGe on insulator (SGOI) structures, which are the basic templates for the strained channel MOSFET's, and the further extensions to the SGOI formation on (110) substrates and the Ge on insulator (GOI) formation are reviewed in this paper. The detail analyses of the phenomenon during the initial stage in the Ge condensation process, in which the fragments of the misfit dislocations, that are formed at the SiGe / SOI interface, rise up resulting the generation of the threading dislocations are quite important, and the controlling of the understood phenomenon by the modification of the condensation recipe brings the successful fabrication of the high quality SGOI substrates with low dislocation density.

Ge channel MOSFETs have recently stirred a strong interest as a promising candidate for high speed MOSFETs beyond strained- Si channels. It has been well recognized, however, that there exist a variety of issues to be solved for realizing Ge MOS technologies. Major critical issues include (1) Gate insulator formation with high quality MIS interfaces (2) High quality GOI or Ge substrate formation (3) Formation of low resistivity S/D junctions (4) CMOS structures and integration. In this paper, these technological problems are addressed and possible solutions for these technological challenges are presented on a basis of our recent research progress.

We report successful fabrication of oxide and nitride interfacial layers on Ge substrates by means of low-temperature plasma processing on Ge substrate. A transmission electron microscope observation revealed that the obtained interfacial layers are atomically smooth. The interface trap density (Dit) was measured for Au/HfO2/Ge metal/insulator/ semiconductor (MIS) structures with oxide and nitride interfacial layers by the ac conductance method. It is found that a minimum Dit value of 1.0x1011 cm-2*eV-1 is obtained for the oxide samples after forming gas annealing (FGA) at 400oC. Significant improvements by FGA on the electrical properties of the samples with nitride interfacial layers, including the reduction of Dit from 1.8x1012 to 1.5x1011cm-2*eV-1, are also demonstrated.