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Ion-implanted profiles in Ge substrates are evaluated and they are reproduced by a tail function with the help of quasi-crystal Lindhard-Scharff-Schiott (QCLSS) theory. Profile parameter database and the through dose are used for predicting ion implantation profiles and related amorphous layer thicknesses in Ge substrates over a wide range of ion implantation conditions.

A novel subband engineering for electron mobility enhancement on (1 1 0) surfaces by utilizing uniaxial tensile strain along the (1 1 0) direction is presented. A 2.0X mobility enhancement is observed with respect to the control, unstrained device.

The device design of 15-nm high-speed source-heterojunction-MOS transistors (SHOTs) on silicon-on-insulator (SOI) substrates with the high-velocity electron injection from the source into the channel regions is examined. Results suggest the achievement of transconductance enhancement of SHOT due to high-velocity electron injection in a whole range of drain bias.

An investigation is made regarding the temperature dependence of hole mobility in the strained SiGe-on-insulator (SGOI) channels fabricated by the Ge-condensation technique is investigated within a wide range of temperatures from 23 to 473 K. Results show a significantly large hole-mobility enhancements in the Ge-rich strained-SGOI-pMOSFETs was observed at T up to 473 K.

The source-heterojunction-MOS-transistor (SHOT) is a novel high-speed MOSFET with relaxed SiGe/strained-Si heterojunction source structures for quasi-ballistic or full-ballistic transistors. An enhanced transconductance in SHOT is observed for high-applied drain voltage.

The threshold-voltage and the short-channeleffects (SCEs) of strained-SOI n- and p-MOSFETs are quantitatively studied by using device simulation. The control of the work function of the gate electrode and the control of bias gate bias are effective for n-MOSFETs and in p-MOSFETs, thicker strained-Si layers and the higher back gate bias are necessary to suppress the buried channel formation.

An investigation on the strain dependence of substrate current and impact ionization efficiency in the strained-Si n- and p-MOSFETs is conducted with the wide range of strain, by utilizing the universal relationship between the impact ionization efficiency and the electrical field in the pinch-off region. The impact ionization efficiency increased with the increase of temperature while its dependence did not exhibit distinct strain dependence.

(110)-surface strained silicon-on-insulator (SOI) n- and p-MOSFETs on (110)-surface relaxed-SiGe-on-insulator substrates with the Ge content of 25% are newly created and investigated. Results confirm that this technology is promising for realizing higher speed scaled CMOS.

Physical mechanisms responsible for the reduction in both electron and hole mobility in strained-silicon-on-insulator (SOI) CMOS devices with thin strained-Si layers are examined. As a result of insight into these mobility lowering mechanisms, a new device design regarding the strained-Si thickness and the Ge content is presented to realize high-speed thin film strained-SOI CMOS devices in 25-nm gate length regimes.

Scaling effects on direct tunneling gate leakage current are analyzed by utilizing new models implemented to perform self-consistent calculation between the direct tunneling, the band-gap narrowing (BGN) and the incomplete impurity ionization. It is found that the scaling of the gate length cannot suppress the gate leak unless the vertical field is strong.

A new concept involving single-layer strained SGOI MOFSETs is described and discussed.

Development of high-performance strained-SOI CMOS devices on thin film relaxed SiGe-on-insulator (SGOI) substrates with high Ge content is discussed.

Electron mobility in the MOS inversion layer of ultra-thin silicon-on-insulator (SOI) devices is investigated to make clear the influence of buried-oxide interface. It is found that the universal thickness is valid for the SOI thickness down to 30 nm, irrespective of the buried-oxide interface quality.

A p-channel strained SOI MOSFETs with a novel double SiGe structures to introduce higher strain in Si channel has been proposed and experimentally studied. The optimized SIMOX annealing temperature and Ge content of SiGe layer for forming the uniform buried oxide layer inside the SiGe layer has been shown.

Research on single electron tunneling devices is examined in detail, with a focus on devices produced with ultrathin films of silicon on insulators.

It has been possible to calculate the ionization rate of phosphorous doped in poly-Si gate and band gap narrowing arising from carrier-carrier interactions and carrier-ion interactions. This work involved reproducing the oxide voltage dependence of the measured tunneling current from the gate in a range of samples with the same tunneling mass.

A new silicon-on-insulator p-metal oxide semiconductor field-effect transistor (SOI p-MOSFET) with a strained-Si channel on insulator (strained-SOI) structure fabricated by SIMOX (separated-by-implanted-oxygen) technology is described. Why such a device is a candidate for high-speed sub-100 nm complementary metal oxide semiconductor (CMOS) applications is explained.

The suppression of the short-channel effect by a bandgap engineering technique is proposed and its effectiveness is evaluated in the case of a SiGe source/drain structure.

The effects of inversion-layer capacitance on supply voltage of n and p MOSFET's are examined.

The inversion-layer capacitance (C(sub inv))in p-channel Si MOSFETs has been studied with focus on the surface carrier concentration dependence. The amount of C(sub inv) and its role on gate capacitance are assessed between electron and hole inversion layers. Results indicate that electrical gate oxide thickness is larger for inversion-layer holes than for inversion-layer electrons for the same gate oxide thickness. It has also been found that the calculated C(sub inv) is an accurate representation of the experimental C(sub inv) over a whole range of surface carrier concentration.

A new I-V model for stress-induced leakage current is reported and compared with the experimental I-V properties. The quantitative model is a modification of the trap-assisted tunneling model, incorporating the energy relaxation of tunneling electrons. In the new model, the energy relaxation is viewed as the change in the energy level of traps prior to and after the captivity of electrons during two-step tunneling.

A new experimental method for investigating the transport characteristics of stress-induced leakage current (SILC) is presented. The quantum results of impact ionization for electrons involved in the SILC process are measured directly from the change in the source and gate currents of p-MOSFETs prior and after stressing. Experimental results show that the measured energy of electrons in the SILC process is lower by approximately 1.5 eV than that expected in the elastic tunneling process.

Conventional admittance spectroscopy is based on the measurement of pn junction admittance or Schottsky diodes made on a substrate. The principle of admittance spectroscopy is applied for the first time ever to the measurement of MOS capacitors manufactured on Si/Si sub 1-xGe sub x/Si double heterostructures. The method was verified through experimentation. A new feature of this MOS capacitor measurement method is that two hetero-interfaces of a double heterostructure can be evaluated separately by controlling the gate voltage.

The inversion-layer capacitance C(sub inv) of n-channel Si MOSFETs depends on the surface carrier concentration N(sub s) and surface quantization. The C(sub inv) depends on the finite effective density of states at low N(sub s). The C(sub inv) depends on the finite inversion-layer thickness at high values of N(sub s). C(sub inv) is affected by quantum mechanics as it has a surface orientation dependence. The experimental values of C(sub inv) agree with the Poisson-Schrodinger calculations.

An examination of the inversion layer mobility in n-channel MOSFETs on Si wafers with (110), (100) and (111) surface orientations reveals that the electron mobilities exhibit universality on (111) and (110) surface orientations only when the parameter eta is 1/3. The electron mobility's dependence on the effective normal field varies for the three surface orientations due to surface roughness scattering. The scattering processes in inversion layer help elucidate the physical formation kinetics of effective normal field and the parameter eta.

Analysis of inversion layer mobility in P- and N-channel Si MOSFETs and the influence of substrate impurities on the layer mobility show that the universality of hole and electron mobilities is valid up to 10 to the 18th power per cubic centimeter and that high substrate impurities change the hole and electron mobilities from the universal curve. The effective normal field influences the universal curves and this dependency is distinct for holes and electrons. The change in the universality occurs at low surface carrier concentrations due to Coulomb scattering.

Remote Coulomb scattering due to gate impurities in poly-Si gate is examined by considering the screening effect due to free carriers in the poly-Si gate. A physics-based screening model, which enables inclusion of the nonuniform carrier distribution in the poly-Si gate into the evaluation of remote Coulomb scattering with high accuracy, is proposed. Based on the proposed screening model, the effect of the nonuniform carrier distribution in the poly-Si gate on the mobility limited by remote Coulomb scattering, μRCS, is quantitatively examined. It is shown that the screening model using the averaged carrier distribution in the poly-Si gate cannot provide the correct description of the behavior of μRCS and the inclusion of the nonuniformity of the carrier distribution is essential for the quantitative evaluation of μRCS. [ABSTRACT FROM AUTHOR]

The electron mobility in ultrathin-body (UTB) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) with SOI thicknesses from 2.3 to 60 nm is measured in a wide temperature range from 25 to 300 K. In UTB SOI MOSFETs with SOI thickness ranging from 5 to 20 nm, a monotonic decrease of electron mobility with a decrease in SOI thickness is observed at room temperature. At extremely low temperature (25 K), however, the electron mobility of UTB SOI MOSFETs with SOI thickness of 5.7 nm is not degraded but is almost the same as that of thick-body SOI MOSFETs. On the other hand, in UTB SOI MOSFETs with SOI thickness ranging from 3.5 to 4.5 nm, an increase of electron mobility with a decrease in SOI thickness is clearly demonstrated at the effective normal field of around 0.3 MV/cm at 300 K. It is concluded that the decrease of electron mobility in SOI thickness ranging from 5 to 20 nm is due to the increased phonon scattering in thinner SOI films. The observed enhancement of electron mobility with decreasing SOI thickness from 4.5 to 3.5 nm is ascribed to the subband structure modulation induced by quantum confinement effects in nanoscale SOI films. The impact of SOI thickness fluctuations on electron mobility and the methods to evaluate the thickness of ultrathin SOI films are also discussed. [ABSTRACT FROM AUTHOR]