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Targeting the simultaneous wireless charging of multiple receiver (RX) coils, we developed a coupling coefficient ( ${k}$ ) sensorless wireless power transfer (WPT) system enabled by the proposed adaptive magnetic field distributor (AMFD) IC. By simply measuring the voltages and currents on the transmitter (TX) side free of knowing the ${k}$ between each pair of coils, the system can optimize the current in each TX coil to optimize the generated magnetic fields at each RX coil to maximize the system efficiency ( $\eta _{\mathbf {SYS}}$ ). A current sensor calibration (CSC) technique was also proposed to guarantee the accurate on-chip current sensing in the AMFD IC. The AMFD IC was fabricated by a $0.18~\mu $ m CMOS process with 1.8 V devices. Owing to the CSC technique, an accurate on-chip current sensing could be performed with a percentage error within ±4.5 %. A WPT system consisting of 2 TX coils driven by 2 AMFD ICs and 2 RX coils was implemented. Experimental results showed that, compared with the conventional WPT method, $\eta _{\mathbf {SYS}}$ in the developed system was increased from 16 % to 65 % with a load power of 276 mW when the RX coils were perpendicular to the TX coils. When the RX coils were parallel to the TX coils, a high $\eta _{\mathbf {SYS}}$ of 78 % was also obtained.

The silicon carbide (SiC) mosfets provide superior properties over conventional silicon power devices with a higher switching speed and lower conduction losses. However, high-frequency switching can cause overshoots, oscillations, and electromagnetic interference (EMI) issues. Because of a fixed gate driving strength, the traditional gate driver struggles with the tradeoff between overshoot and switching loss (switching speed). To improve the switching performance of the SiC power devices, an active gate driver (AGD) integrated circuit is proposed using a 0.18-μm CMOS HV BCD process is proposed in this article. Instead of requiring a separate programmable logic board, the controller circuits and driving stage are integrated on a chip. The proposed gate voltage sensing technique detects the slope difference of the gate voltage and generates the appropriate gate driving signals without detecting the SiC mosfet ID and VDS information. The area and cost are reduced by removing the high-voltage sensing circuit for ID and VDS detection. The proposed AGD can also attenuate the oscillations of ID and VDS, further reduce the EMI noise induced by high switching speed. In addition, the experimental results show that the proposed AGD can be applied to different SiC power mosfets.

This letter presents a high-power-density point-of-load dc–dc converter for 12/24 V input applications, using the proposed high voltage-low voltage separated hybrid switched-capacitor (SC) topology. By incorporating inductors between the SC networks in HV/LV domains, the design achieves reduced inductor dc current (IL,DC) at small voltage conversion ratios (VCRs), optimized switching and conduction losses, and extended duty ratio range, enabling the use of small-sized inductors with higher dc resistance and resulting in a compact system volume. LV switches handle most of the current conduction, reducing switching losses and silicon area for higher on-chip power density. The fabricated converter, using a 180-nm BCD process, generates 0.8–1.8 V output from 12/24 V inputs with a 3-A maximum load. Measured results show total IL,DC of 1.2 A at VCR 0.075 and 2 A load. The converter achieves a peak power density of 355 mW/mm3 with a power passive volume of 15.2 mm3. Peak efficiencies are 85% at 12 V input and 84.2% at 24 V input.

This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH) converter at the input, and a continuous-current-input SC (CISC) stage at the output, achieves superior performance in reducing the inductor DC current ( $I_{\mathrm {L,DC}}$ ) compared to the existing single-inductor two-flying-capacitor ( $1L$ - $2C_{\mathrm {F}}$ ) converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to 3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is 93% and the on-chip current density is 0.638A/mm2. The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200 $\text{m}\Omega $ .

This paper introduces a 6.78-MHz wireless power transfer (WPT) system for implantable medical devices (IMDs). The proposed dual-output resonant current-mode (RCM) rectifier cumulates energy from loosely-coupled coils and generates two output voltages (VH = 3-V, VL = 1.8-V) regulated by adaptive power control (APC) and local-loop power control. Due to transmission power regulation (TPR), the transmitter ( $T_{X}$ ) delivers appropriate power to the receiver ( $R_{X}$ ) to realize global-loop power control. Thus, the power transfer efficiency (PTE) is improved, especially under light load. Furthermore, zero-voltage switching and zero-current switching techniques enhance ${R} _{X}$ power conversion efficiency (PCE). $T_{X}$ and $R_{X}$ chips were fabricated in a 0.18- $\mu \text{m}$ CMOS process. The measurement results show that the proposed WPT system successfully regulates outputs at VH = 3-V and VL = 1.8-V at a 1.5-cm coupling distance. With the proposed TPR, PTE is improved by 28.2% at PTOTAL = 1.6-mW, and input power is reduced by 94.8% at PTOTAL = 1-mW. The measured peak PCE and peak PTE are 85.1% and 31.3% at a coil distance of 10-mm, respectively.