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This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access time with a scaled CMOS in IOs. The power supply for IO buffers, namely, VDDQ, decreases from 3 V to 1.2 V, accordingly. In this paper, the way in which a reduction in VDDQ can contribute to power reduction in the BL path is discussed and validated. Conventionally, a BL voltage of about 0.5 V has been supplied from a supply voltage source (VDD) of 3 V. The BL path power can be reduced by a factor of VDDQ to VDD when the BL voltage is supplied by VDDQ. To maintain a sense margin at the sense amplifiers, the supply source for BLs is switched from VDDQ to VDD before sensing. As a result, power reduction and an equivalent sense margin can be realized at the same time. The overhead of implementing this operation is an increase in the BL access time of about 2% for switching the power supply from VDDQ to VDD and an increase in the die size of about 0.01% for adding the switching circuit, both of which are not significant in comparison to the significant power reduction in the BL path power of the NAND die of about 60%. The BL path is then designed in 180 nm CMOS to validate the design. When the cost for powering the SSD becomes quite significant, especially for data centers, an additional lower voltage supply, such as 0.8 V, dedicated to BL charging for read and program verifying operations may be the best option for future applications. [ABSTRACT FROM AUTHOR]

This paper proposes a circuit model of a cross-coupled CMOS AC–DC charge pump (XC–CP) operating in the subthreshold region. The aim is to improve the efficiency of designing XC–CPs with a variety of specifications, e.g., input and output voltages and AC input frequency. First, it is shown that the output resistance (Ro) of XC–CP is much higher than those of CPs with single diodes (SD–CP) and ultra-low-power diodes (ULPD–CP) as charge transfer switches (CTSs). Second, the reason behind the above feature of XC–CP, identified by a simple model, is that the gate-to-source voltages of CTS MOSFETs are independent of the output voltage of the CP. Third, the high but finite Ro of XC–CP is explainable with a more accurate model that includes the dependence of the saturation current of MOSFETs operating in the subthreshold region on the drain-to-source voltage, which is a function of the output voltage of CP. The model is in good agreement with measured and simulated results of XC–, SD–, and ULPD–CPs fabricated in a 250 nm CMOS. [ABSTRACT FROM AUTHOR]

This paper pursued both the lower operating power limit and small area of on-chip rectifiers for microwave wireless power transfer (MWPT). RF–DC charge pump rectifiers can operate in the fast switching limit at a high frequency of 920 MHz even with a small stage capacitor Cin of 100 fF, which contributes to an area reduction in the on-chip rectifiers. Circuit design starts with Cin determined as small as possible, followed by the determination of switching transistors and the number of stages. Even at an extremely low input power of 1 μW, wiring resistance in RF inputs is critical. Routing of the RF inputs is designed in line with stage capacitors. Bonding pad structure also affects the lower input power limit. Ground-shielded pad design can reduce the lower limit. Various types of RF–DC charge pump rectifiers are fabricated in 65 nm CMOS. An ultra-low-power diode RF–DC charge pump rectifier with 32 stages had a lower input power limit of −31.7 dBm at an output voltage of 1.0 V. Its small silicon area of 0.011 mm2 allows RF–DC rectifiers to be integrated in sensor ICs. More advanced technology providing MIM capacitors with higher capacitance density and placing switching MOSFETs under the MIM capacitors will further reduce the area of RF–DC charge pump rectifiers, allowing them to be integrated in sensor ICs. [ABSTRACT FROM AUTHOR]