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With the advance of various energy harvesting and storage devices, self-powered wearable systems have gained significant interest in the past few years. In addition, the growing focus on fibers with digital devices is driving the potential for fabrics with digital systems for health monitoring and human-machine interfaces. While such digital-enable fabric systems consist of various distributed digital devices, a low-power serial communication component is in high demand. The standard Serial Peripheral Interface (SPI) commonly used in device connection is unsuitable for communication in fiber because the bit width of the slave select signal (SS) increases with the number of networked devices. To address this research gap, we propose using Inter-Integrated Circuit (I2C) for communication in fiber and presenting the SPI-I2C Protocol Converter chip for data transfer from the SPI to the I2C bus. Our research involves designing and implementing a low-power I2C module with tunable frequency, data width, and output voltage. The I2C module on the chip can work at 0.4 V supply voltage with only 2.6 nW static power. In addition, we designed the I2C controller on the chip that can adaptively adjust the drive capability to balance power consumption and reliability when more devices are connected. Finally, we integrate the I2C module into the System-on-Chip (SoC) using the ARM Advanced Peripheral Bus (APB) to complete the digital-enabled fabric system.

Although India has achieved considerable capability in electronic chip design, but developing the infrastructure for capital-intensive semiconductor fabrication remains a challenge. The rising domestic and global demand for electronics products, the need of enhancing the country's high-technology talent pool, employment generation, and national security concerns dictates the Indian Government's heightened efforts in promoting electronics hardware manufacturing in the country. A recent milestone in this regard is the setting up of 180nm CMOS fabrication facility at SCL, Chandigarh. The Multi Project Wafer runs of this indigenous foundry promises to be a relatively cost-effective option for Indian academic and R&D institutions in realizing their designed VLSI circuits. Written from the perspective of an Analog VLSI designer, this tutorial paper strives to provide all the requisite information and guidance that might be required in order to prepare chip designs for submission to SCL for fabrication., This is preprint of article accepted for publication in IETE Journal of Education, published by Taylor & Francis. Available online at: https://doi.org/10.1080/09747338.2019.1657787

Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.

In urgent post tape-out, runtime is a big challenging for backend layers’ OPC (Optical Proximity Correction). Sometimes there is no extra time for OPC to clean all the ORC (Optical Rule Check) hotspots with recipe tuning. So the repair flow is the good choice, the repair flow is costly final step, especially for Metal layer’s. In some challenging case, there will be thousands or millions hotspots which can’t pass various ORC criteria need to be into repair flow, thus not only makes our system overloading and the runtime is unacceptable. There are many applications for Machine Learning (ML) in IC field, such as ML-OPC, ML-Hotspot detection and ML-SRAF etc. And Calibre ML-OPC has powerful functionality which fits the requirement of repair flow very well. In this paper, we will introduce how to use Calibre ML-OPC to reduce the most of the defects to speed up the repair process and demonstrate the benefit comparing to the traditional repair flow.

The often touted attractive attributes of printed/organic electronics are its mechanically flexible form-factor, low-cost, green, on-demand printing, scalability, low-power operation, and intelligence (signal processing) – ideally, the creation of intelligent lightweight electronics printed by simple ubiquitous printing processes, and integrated into new ways to exploit its mechanically flexible form-factor. Printed/Organic Electronics, now an industry on its own right and recognized as one of the key technological enablers for the Internet of Things, is largely complementary to silicon because the printed transistors are slow and the printed elements are large. The sanguine projected growth of the $29 B market today to $73 B by 2027 assumes that ‘intelligence’ (analog, mixed-signal and digital signal processing) would be realizable. Nevertheless, many of the said attributes of printed/organic electronics remain a challenge. In this paper, we exemplify this with a comprehensive and critical review and tabulation of the state-of-the art printed digital, analog, and mixed-signal circuits. We further review the application space of printed/organic electronics and the supply chain, including their classifications and delineate the associated challenges in each constituent chain. These challenges, largely unresolved, are indeed formidable, and are discussed with a critical circuits and systems perspective. Our review depicts that contemporary design philosophies and methodologies for silicon are largely inadequate for printed/organic electronics. To this end, we discuss esoteric analog and digital design philosophies and methodologies, with emphasis on co-design and co-optimization between the different constituent supply chains that may potentially circumvent the said formidable challenges, and discuss the associated penalties thereto.

For several years, micro-electro-mechanical systems (MEMS) have been experiencing dynamic and sustained growth. This development is mainly driven by the automotive industry. One example of such a growing market is tire pressure monitoring systems (TPMS). Initiated by legal regulations in the USA and the EU (in China, laws on the mandatory use of TPMS will apply from 2020), the market has experienced its own momentum as a result of the continuous development of TPMS. In addition, the positive market development is reinforced by the continuously decreasing costs of sensors. Costs related to sensor development are the development costs, which are reflected in the time from the customer inquiry or specification to the tape out. Although the design of MEMS has been the subject of research and development activities for years, there is still a gap compared to a typical IC design environment. This chapter provides an overview of the current state of MEMS design. Using the example of a three-dimensional (3D) acceleration sensor, new approaches for efficient design and layout are shown.

Silicon Photonics design layouts require use of curved shapes, since many of the structures built to route light through silicon are designed to curve smoothly to minimize the loss of signal strength. The design-to-silicon flow involves steps like Design Rule Checking (DRC), Optical Proximity Correction (OPC), Mask Rule Checking (MRC), Mask Process Correction (MPC), mask data fracture, mask writing and mask inspection. All of these steps involve software and techniques that have evolved over decades of use for predominately orthogonal design geometries composed of vertical and horizontal edges. In many cases, these tools and process steps will perform poorly or fail if they are used on free form curvilinear layouts – unless changes are made to accommodate the curvilinear designs. In this paper, we describe challenges in various steps of the design-to-silicon flow associated with supporting curvilinear photonics design layouts. We first present two flow alternatives, which we call “manhattanization” and “free form”. The manhattanization flow is where angles or curved layout edges are converted to short vertical and horizontal fragments closely matching the design intent. The advantage of the manhattan approach is that DRC, OPC, MRC and MPC decks designed for use on orthogonal CMOS designs can be used on photonics content that has been manhattanized. We present examples of layouts where the manhattan approach causes problems in several phases of the tapeout flow. We also present an example of a free form tape out flow, with particular focus on the unique challenges faced in correcting for different wafer processing steps in the OPC recipes. We also discuss some of the existing literature offering ideas on how to best manage free form layouts in OPC and mask data preparation. Ultimately, the goal of these data operations is to enable creation of a photomask for use as a master template in the chip production; since these mask writers almost exclusively operate with rectilinear data, the designs must ultimately be Manhattanized. We will explore the benefits, challenges, and drawbacks to manhattanizaiton specifically during mask making as well. The latter portion of the paper presents some of the challenges faced in mask making for free form photonics designs. We discuss the role that MPC plays in photonics mask production, where many features are sufficiently large to make MPC unnecessary, and we look some examples of more advanced photonics designs where MPC may need to play a role. We explain the challenges in trying to define and enforce MRC rules on curvilinear content to ensure mask inspectability and manufacturability. We describe the design and use of a programmed defect inspection test mask designed to formulate some simple MRC rules for free form mask designs. We demonstrate the linkage between curvilinear DRC and MRC, as the techniques and challenges faced in both areas are very similar. We also explore the relationship between the manhattanization and mask operational and performance metrics, such as data volume, write time, image fidelity, and design intent fidelity when going from manhattanized mask shapes to free form mask shapes for photonics layouts.

Standard cell library is the basic for building blocks and SoC (system on chip). And design in current standard cell library always meets the most critical design rule, leading to tight lithography process window and hotspots easily. Besides, passing design rule check (DRC) cannot fully guarantee manufacturability. Lithography simulation check is an essential check item before tape out. It is significant to qualify the standard cell library at the most possible early stage in order to avoid design rework during the tape-out stage. For 14nm technology and below, hotspots appear both inside cell, abut regions of standard cells and pins for routing. Therefore, our paper puts forward a fast DFM-driven standard cell qualification approach to detect the hotspots inside cell and the potential defects from special kinds of pins and abutting standard cells. It can discover problems early and set constraints for placement and routing as early as possible for a fast product yield ramp-up.

A amorphous-indium-gallium-zinc-oxide (a-IGZO) TFT integrated 9T2C gate driver on array (GOA) circuit with a novel inverter structure has been proposed. This inverter contributes significant to the reduction of power than traditional inverter structure. To testify the function, the circuit was placed in an active-matrix organic light-emitting diode (AMOLED) display. After the panel was tape out, the circuit exhibited stable out-put signals.

In the recent years, there has been rapid increase in complexity of System on Chip designs. As the functionality of the chip increases, design and verification runtime also increases. Physical design involves both design and verification of the layout. Thus major challenge for semiconductor industries is that the design of chip and its verification has to be done efficiently keeping in mind the stringent tape out schedule. Power consumption is of primary concern in the semiconductor industry as the power consumed by the chip directly affects the chip’s performance and lifetime. Specifically for sub nanometer technologies, leakage power consumption is dominant. Thus there is a need for reduction in leakage power consumption by implementation of appropriate power gating techniques in the design flow. In the proposed design flow, using multi threshold cells, this has been addressed and a novel low power design is implemented using 16nm FinFET technology through power switches in the power domain. For design implementation various tools such as Innovus, IC Compiler II and Calibre Design RVE is used in this paper.

Foundry FAB manufactures a variety of semiconductor products with adverse mixture of process flows. For process control, it is a challenge to define some critical dimension measurement items target of each unique product characteristic before new tape out (NTO). After some wafers pilot run completed, a proper measurement target was defined. The engineers have to waste valuable resources for measurement retargeting and expense extra process time to validate these changes satisfied.As we know, the mask layout pattern density (PD) has highly correlated with measurement target. However, traditional regression model results can not satisfy advanced processes requirements. In this study, we proposed new factors, including local pattern density, line density and traditional global pattern density (GPD) into model. Furthermore, the regression model was refined with machine learning, k-NN (k-th Near Neighbor), to enhance the prediction accuracy for NTO measurement target. The simulation result showed average prediction accuracy come up to 85% above, compared with previous 61% only. Even some layers accuracy achieved 95% above.

The effort in designing analog/mixed-signal (AMS) integrated circuits is characterized by the largely manual work involved in the design of analog cells and their integration into the overall circuit. This inequality in effort between analog and digital cells increases with the use of modern, more complex technology nodes. To mitigate this problem, this paper presents four methods to improve existing mixed-signal design flows: (1) automatic schematic generation from a system-level model, (2) flexible automatic analog layout generation, (3) constraint propagation and budget calculation for dependency resolution, and (4) verification of nonfunctional effects. The implementation of these steps results in a novel AMS design flow with a significantly higher degree of automation.

the model and design of the IP core of APB interfacing with SPI is presented. In this work, the SPI interface can send or receive data from a single slave and efficient APB-SPI controller with flexible data width and frequency. The SPI is simulated by ModelSim, QuartusLite 16 and will be synthesized to produce the gdsii file for tape out. The findings of the SPI interface to send or receive data from a single slave and efficient APB-SPI controller with flexible data width and frequency is proven for maximum frequency of 16 MHz.

At Ghent University, we have built a course curriculum on integrated photonics, and in particular silicon photonics, based on interactive Jupyter Notebooks. This has been used in short workshops, specialization courses at PhD level, as well as the M.Sc. Photonics Engineering program at Ghent University and the Free University of Brussels. The course material teaches the concepts of on-chip waveguides, basic building blocks, circuits, the design process, fabrication and measurements. The Jupyter notebook environment provides an interface where static didactic content (text, figures, movies, formulas) is mixed with Python code that the user can modify and execute, and interactive plots and widgets to explore the effect of changes in circuits or components. The Python environment supplies a host of scientific and engineering libraries, while the photonic capabilities are based on IPKISS, a commercial design framework for photonic integrated circuits by Luceda Photonics. The IPKISS framework allows scripting of layout and simulation directly from the Jupyter notebooks, so the teaching modules contain live circuit simulation, as well as integration with electromagnetic solvers. Because this is a complete design framework, students can also use it to tape out a small chip design which is fabricated through a rapid prototyping service and then measured, allowing the students to validate the actual performance of their design against the original simulation. The scripting in Jupyter notebooks also provides a self-documenting design flow, and the use of an established design tool guarantees that the acquired skills can be transferred to larger, real-world design projects.

Data volume and average data preparation time continue to trend upward with newer technology nodes. In the past decade, with file sizes measured in terabytes and network bandwidth requirements exceeding 40GB/s, mask synthesis operations have expanded their cluster capacity to thousands and even 10s of thousands of CPU cores. Efficient, scalable and flexible management of this expensive, high performance, distributed computing system is required in every stage of geometry processing - from layout polishing through Optical Proximity Correction (OPC), Mask Process Correction (MPC) and Mask Data Preparation (MDP) - to consistently meet tape out cycle time goals. The MDP step, being the final stage in the entire flow, has to write all of the pattern data into one or more disk files. This extremely I/O intensive section remains a significant portion of the processing time and creates a major challenge for the software from a scalability perspective. It is important to have a comprehensive solution that displays high scalability for large jobs and low overhead for small jobs, which is the ideal behavior in a typical production environment. In this paper we will discuss methods to address the former requirement, emphasizing the efficient use of high performance distributed file systems while minimizing the less scalable disk I/O operations. We will also discuss dynamic resource management and efficient job scheduling to address the latter requirement. Finally, we will demonstrate the use of a cluster management system to create a comprehensive data processing environment suitable to support large scale data processing requirements.

As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.

The goal of a foundry partner is to deliver high quality silicon product to its customers on time. There is an assumed trust that the silicon will yield, function and perform as expected when the design fits all the sign-off criteria. The use of Intellectual Property (IP) blocks is very common today and provides the customer with pre-qualified and optimized functions for their design thus shortening the design cycle. There are many methods by which an IP Block can be generated and placed within layout. Even with the most careful methods and following of guidelines comes the responsibility of sign-off checking. A foundry needs to detect where these IP Blocks have been placed and look for any violations. This includes DRC clean modifications to the IP Block which may or may not be intentional. Using a pattern-based approach to detect all IP Blocks used provides the foundry advanced capabilities to analyze them further for any kind of changes which could void the OPC and process window optimizations. Having any changes in an IP Block could cause functionality changes or even failures. This also opens the foundry to legal and cost issues while at the same time forcing re-spins of the design. In this publication, we discuss the methodology we have employed to avoid process issues and tape-out errors while at the same time reduce our manual work and improve the turnaround time. We are also able to use our pattern analysis to improve our OPC optimizations when modifications are encountered which have not been seen before.

Virtual prototyping of Analog/Mixed-Signal (AMS) systems is a key concern in modern SoC verification. Achieving first-time right designs is a challenging task: Every relevant functional and non-functional property has to be examined throughout the complete design process. Many faulty designs have been verified carefully before tape out but are still missing at least one low-level effect which arises from interaction between one or more system components. Since these extra-functional effects are often neglected on system level, the design cannot be rectified in early design stages or verified before fabrication. We introduce a method to determine system acceptance regions tackling this challenge: We include extra-functional effects into the system models, and we investigate their behavior with parallel simulations in combination with an accelerated analog simulation scheme. The accelerated simulation approach is based on local linearizations of nonlinear circuits, which result in piecewise-linear systems. High-level simulation speed-up is achieved by avoiding numerical integration and using parallel computing. This approach is fully automated requiring only a circuit netlist. To reduce the overall number of simulations, we use an adaptive sampling algorithm for exploring systems acceptance regions which indicate feasible and critical operating conditions of the AMS system.

The change from isomorphic to anamorphic optics in high numerical aperture (NA) extreme ultraviolet (EUV) scanners necessitates changes to the mask data preparation flow. The required changes for each step in the mask tape out process are discussed, with a focus on optical proximity correction (OPC). When necessary, solutions to new problems are demonstrated, and verified by rigorous simulation. Additions to the OPC model include accounting for anamorphic effects in the optics, mask electromagnetics, and mask manufacturing. The correction algorithm is updated to include awareness of anamorphic mask geometry for mask rule checking (MRC). OPC verification through process window conditions is enhanced to test different wafer scale mask error ranges in the horizontal and vertical directions. This work will show that existing models and methods can be updated to support anamorphic optics without major changes. Also, the larger mask size in the Y direction can result in better model accuracy, easier OPC convergence, and designs which are more tolerant to mask errors.

Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging presents the electromagnetic modelling and design of three major electromagnetic compatibility (EMC) issues related to the high-speed printed circuit board (PCB) and electronic packages: signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI). The emphasis is put on two essential passive components of PCBs and packages: the power distribution network and the signal distribution network. This book includes two parts. Part one talks about the field-circuit hybrid methods used for the EMC modeling, including the modal method, the integral equation method, the cylindrical wave expansion method and the de-embedding method. Part two illustrates EMC design methods and explores the applications of novel metamaterials and two-dimensional materials on traditional EMC problems. This book is designed to enhance worthwhile electromagnetic theory and mathematical methods for practical engineers and to train students with advanced EMC applications.

It is well known that ASICs have orders of magnitude higher power efficiency than general propose processors. However, due to the high engineering and manufacturing cost only handful of companies can afford to design ASICs. To reduce this cost numerous high-level synthesis tools have emerged since last 2-3 decades. In spite of these tools, ASIC design is still considered expensive because they fail to accurately predict the cost metrics. The inaccuracy is costly as it results in multiple iterations between RTL, logic synthesis, and physical design. The major reason behind this inaccuracy, at high level, is unavailability of information like wiring, orientation, and placement of hardware blocks. To tackle this issue, recent works have proposed to raise the abstraction of the physical design from standard cells to micro-architectural blocks physically organized in a structured grid based layout scheme. While these works have been successful in accurately predicting area and timing, to the best of our knowledge their effectiveness in accurately estimating power is yet to be determined. SiLago-CoG provides an efficient technique to characterize these blocks and estimate power at high level. Simulation and synthesis results reveal that SiLago-CoG provides up to 15X better power estimates in 680X less time at the cost of up to 50% additional area, compared to state-of-the-art.

The authors present a method, an algorithm and a program, designed to determine the optimal size of printed circuit boards (PCB) of mechanical structures and different kinds of electronic equipment. The PCB filling factor is taken as an optimization criterion. The method allows one to quickly determine the dependence of the filling factor on the size of the PCB for various components.

Simulation is a very powerful tool for hardware designers. It generally allows the preliminary evaluation of a chip’s performance before its final tape out. As security against side-channel attacks is an increasingly important issue for cryptographic devices, simulation also becomes a desirable option for preliminary evaluation in this case. However, its relevance highly depends on the proper modeling of all the attack peculiarities. For example, several works in the literature directly exploit SPICE-like simulations without considering measurement peripherals. But the outcome of such analyses may be questionable, as witnessed by the recent results of Renauld et al. at CHES 2011, which showed how far the power traces of an AES S-box implemented using a dynamic and differential logic style fabricated in 65nm CMOS can lie from their post-layout simulations. One important difference was found in the linear dependencies between the (simulated and actual) traces and the S-box input/output bits. While simulations exhibited highly non-linear traces, actual measurements were much more linear. As linearity is a crucial parameter for the application of non-profiled side-channel attacks (which are only possible under the assumption of “sufficiently linear leakages”), this observation motivated us to study the reasons of such differences. Consequently, this work discusses the relevance of simulation in security evaluations, and highlights its dependency on the proper modeling of measurement setups. For this purpose, we present a generic approach to build an adequate model to represent measurement artifacts, based upon real data from equipment providers for our AES S-box case study. Next, we illustrate the transformation of simulated leakages, from highly non-linear to reasonably linear, exploiting our model and regression-based side-channel analysis. While improving the relevance of simulations in security evaluations, our results also raise doubts regarding the possibility to design dual-rail implementations with highly non-linear leakages.

Printed circuit boards now need to come in all shapes and sizes - and so the computer-based tools available to design them have to offer enhanced flexibility and functionality.

This paper presents a data analytics approach for recovering test-pad information from images of printed circuit boards. The main aim is to obtain highly accurate information as input to a robotic flying probe tester. Such a tester is a mechatronic system that is able to perform a great variety of diagnostic testing on printed circuit boards without any additional circuit board documentation. In this work, a two-stage clustering process was applied on a dataset with 71040 pixel records obtained from an electronic circuit board image. In total, the method discovered 128 locations on the circuit board that are potentially the test pads. Visual inspection found that all the 120 legitimate test pads on the circuit board were retrieved. The other eight locations were not really test pads and were removed (i.e., Recall = 100%, and Precision = 93.25%). We propose this image analytics approach as an effective way to speed up the recovery of test-pad locations from printed circuit boards.

Inverse Lithography Technology (ILT) is gaining acceptance as part of a comprehensive OPC solution especially as a repair technique to locally improve process window where conventional OPC does not have enough degrees of freedom to produce acceptable results. [1] Since ILT is significantly more computationally intensive than conventional OPC, a localized application of ILT does not significantly increase OPC cycle time. As ILT methods mature and become more efficient, combined with the availability of huge compute clusters for post tape out data processing, the possibility of full-field ILT OPC could soon become reality. Full-field ILT OPC may provide improved process window and greater layout flexibility as long as multi-patterning methods with 193 nm exposure wavelength remain the primary lithography strategy for advanced technology nodes. Due to limitations of photomask lithography tools that prevent efficient exposure of non-Manhattan shapes, ILT OPC output is typically post-processed to conform to mask MRC rules, rendering the raw all-angle features to a Manhattanized equivalent. Previous comparisons of raw vs Manhattan ILT OPC at earlier nodes have shown that a Manhattanized output can be made to print on wafer with equivalent process window while conforming to mask manufacturing rules.[2,3,4] In this paper we use wafer-level lithography simulation to compare raw vs Manhattanized ILT output based on current advanced nodes and MRC rules. We expand this study to include a mask model to ensure that mask corner rounding effects are considered.

This paper provides several methods by using Synopsys IC Compiler (ICC) to optimize Clock Tree Synthesis (CTS), reasonable floorplan, parameter constraint, manual specification, Engineering Change Order (ECO) included. An IC smartcard named BES1300 using 0.18µm EFLASH 2P4M technology is applied to verify the propose methods. Optimizing timing manually is mainly described. Testing results show that hold violation improves 34% and area reduces 9%. The validity of methods is proved by the tape out result.

Objectives: To design the 16bit Reduced Instruction Set Computing (RISC) processor using the Verilog Hardware Description Language (HDL). Methods: This is a 4 stage pipelined processor with idle state, fetch state, decode state, and execute state. Here the write back stage is also performed in the same execution state. The physical design of the processor is done by floor plan followed by placement and routing process. In the placement process iteration is continued till it meet the timing constraints. Findings: In the floor plan we decide the utilization factor, width and height of the core and die, apart from that we decide the location of the IO Pads. The location of the preplaced cells and standard cell placement are find during the placement process. In the placement process if the congestion is huge then the hard blockage placement is done to eliminate the congestion. During the trail route the tool does the timing analysis using the ideal clock, which is then replaces the ideal clock with the real clock after the clock tree synthesis. This process is followed by the spare cells placement in the empty region where we can replace these cells with the logic cells in future; this step in the physical design procedure is known as Engineering Change Order (ECO). During the tape out process if the timing is not met we may not do the placement and routing process from the starting step so we go for the ECO where we can replace the cells with the other cells of same functionality to reduce the delay in order to remove the setup slack. Applications: RISC processors are used in wide range of applications such as mobile phone, tablet computer, super computers etc, RISC processors are also used in signal processing applications such as convolution, correlation etc.

Flexible electronics is a promising technology for wearable applications. The flexible printed thin-film transistor (TFT) circuits, however, often suffer from large process variations and inferior long-term reliability. This paper describes recent progress on robust printed circuits, including a novel design style known as Pseudo-CMOS, which was invented [1] to tackle design challenges for flexible TFT circuits. With post-fabrication tuning capability, Pseudo-CMOS can survive large process variations which are inevitable for the low-cost printing process. Furthermore, degradation of circuit performance, either due to variations or aging, can be recovered by means of an external tuning circuit. The paper also illustrates some design examples of Pseudo-CMOS circuits for applications to energy [2], healthcare [3], biomedical [4], and near-field communication (NFC) tags [5], [6].

Software design programs often assist RF/ microwave engineers in creating high-frequency printed circuit boards (PCBs). A multitude of commercial software tools are available, from electromagnetic (EM) simulation programs to circuit layout and complete system simulators. Both engineers and software tools try to forecast the effects of various circuit- and material-based parameters, but some factors may be overlooked or simply not well enough understood to be properly accounted for in a software simulation of a PCB design. This article intends to help RF/microwave PCB designers better understand the different influences affecting high-frequency PCB loss performance, such as copper roughness, solder mask, plated finishes, and circuit configurations, and how to more accurately predict their effects on final PCB insertion-loss (IL) performance.

The VLSI placement problem is to place the objects into fixed die such that there are no overlaps among the objects and some cost metric such as wire length and routability is optimized. For this purpose A new routing method is used - called , A Deep sub-wavelength lithography, (using the 193nm lithography to print 45nm, 32nm, and possibly 22nm integrated circuits), is one of the most fundamental limitations for the continuous VLSI scaling,. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical design step before tape out. This paper will discuss some recent advancement of lithography friendly routing from post-routing hotspot fixing (construct by- correction) to during-routing hotspot avoidance (correct-by construction) guided by various lithography metrics.

There are many ways to manufacture Micro Electro-mechanical Systems (MEMS). For thin-film fabrication of integrated MEMS parts, several different techniques (like etching and electroplating) are applied. Typically, the whole fabrication of MEMS devices is conducted on a carrier wafer, which is fixed and bonded on a Printed Circuit Board (PCB). This procedure is complex and time-consuming. Also the system integration of the bonded MEMS faces difficulties. To reduce complexity and time, as well as to facilitate its integration, a new processing approach is investigated at the Institute for Micro Production Technology at the Leibniz Universität Hannover. The approach chosen for fabrication of electro-magnetic MEMS devices is the application of PCB as carrier wafer. After preparation of the PCB, the MEMS components can be structured by thin-film technology directly on the PCB using the laminated Cu layer. This fabrication procedure allows integrating the MEMS components into the system from the beginning.

In this paper, CASCADE, a standard supercell-based design methodology, its supporting automated design flow, and associated design tools, are presented for 3D implementations of a class of interconnect-heavy application-specific very large-scale integrated circuits. In CASCADE, a system is first partitioned and synthesized using standard 2D design tools to a set of supercells with the same height and varying widths. With this, the 3D design is reduced to 3D supercell placement and 3D-via assignment. A congestion-driven simulated-annealing method is used to find a 3D placement of supercells to minimize the total wire length, the longest wire length, and the number of 3D vias and routing density. To efficiently estimate the routing density of a 3D grid space within the optimization loop, a simple probabilistic congestion model with an incremental congestion computation has been developed. Once the supercell placement is fixed, the problem of assigning 3D vias to accomplish minimal 2D routing densities and uniform 3D-via distribution is solved by an efficient min-cost-max-flow method. The proposed methods have been implemented and tested on a set of ISPD98 circuit benchmarks. Experimental results have shown that the proposed congestion-driven 3D supercell placement and flow-based 3D-via-assignment tools have yielded satisfactory placement with small-area, low-congestion, short-wire-length, few, and uniformly distributed 3D vias. Furthermore, an excellent correlation between routing-density estimation by our model and the actual routing performed by a commercial router has been observed. We have applied the proposed 3D design methodology, tools, and flows to tape out an over 4-million-gate low-density parity-check decoder in a three-tier 0.18- fully depleted silicon-on-insulator 3D CMOS process manufactured by MIT Lincoln Laboratory. The postlayout simulation of this DRC-clean layout design showed an about ten times improvement on the power-delay-area product compared to a 2D implementation in the same process.

Our team has been developing a System on a Chip (SoC) and is using Synopsys VDK to accelerate both software development and hardware verification. We will discuss how VDK has helped us achieve our primary goal of starting software development and testing prior to design fabrication and our secondary goal of testing our RTL with software. The platform creation process and our transition from RTL-only to Transaction-Level-with-RTL co-simulations will be briefly discussed to provide background. We will also compare our efforts prototyping our design on FPGAs to our experience using VDK. The integration of VDK with an RTL simulator has provided a good balance of simulation speed and visibility down into the design and our engineers have been able to run design validation testing (DVT) software on a large portion of our final RTL prior to our tape out.

Today's semiconductor manufacturing trends are increasingly influencing hardware design techniques, tools, and methodologies. We analyze these trends and describe their effects on design methodologies. These effects clearly include impacts on yield optimization resolution enhancement.

Reviews the equipment and processing challenges involved in the initial stages of the manufacture of large area back plane printed wiring boards and describes some of the techniques employed by APW Electronic Solutions.

To improve the design flow for silicon and other photonics technologies, companies from the photonics [1, 2] and electronics design automation [3] domain collaborate, to improve the integration of simulations, layout, verification and design rule checking.

This paper presents a top-down approach for the design process of digital Application Specific Printed Electronics (PE) Circuits (ASPECs); from functionality specification at circuit level (i.e. HDL), through the optimization of combinational circuitry (represented by their logical equations), according to the PMOS-based technology that will be used to build a set of Standard Cells (SC) or use a predesign Inkjet Gate Array (IGA), down to the Place and Route to get the final circuit layout. This process will use the technology coming from the Centre for Process Innovation (CPI). This methodology maps the existing ASIC one by updating design styles and cost functions. Thus, it is portable to different Printed Electronics processes, using state-of-the-art logic synthesis EDA/software tools being the main optimization goal the transistor count. Main reason is that printed electronics technologies show low density and not such high yield compared to traditional Silicon-based microelectronics. To illustrate this methodology, we use the design and implementation of the TicTacToe game to be implemented together with flexible textile pressure sensor and lighting.

Mixed-signal design becomes more and more popular nowadays, designers are required to quickly integrate IPs and run through the design flow to tape out in short time, so a fast and accurate design flow will be critical to ensure the success of the project. In this paper, a UVM-based methodology for mixed-signal sub-system verification of wireless power receiver family MCU is introduced. As standard digital functional verification method, UVM co-works with analog design which greatly improves the verification efficiency and quality. The model-based verification approach also helps build a scalable and re-usable framework, in which coverage driven verification (CDV) is achieved with automatic stimulus generation, analog assertions are also used to monitor and verify mixed-signal system behavior automatically.

This paper presents an investigation about the ideal composition of cell libraries to be used for digital Application Specific Printed Electronics Circuits (ASPECs). Printed/organic/flexible electronics is becoming more and more important over the last years, and it seems that the industry will continue growing as new possible applications arise, and the existing ones are being improved due to better designs and fabrication processes, even moving towards integrating logic circuitry together with sensors and actuators. This paper presents considerations for developing (ASPECs), trying to keep a similar approach to the typical ASIC procedures. The work presented herein adopted a cell-based design methodology addressed to printed electronics (PE) designs. Such methodology allows us to propose a design flow for PE similar to the VLSI design flow, comprising logic synthesis, mapping, placement, and routing. In order to evaluate different library compositions, a set of benchmark has been mapped with six different combinations of mapping tools and associated libraries. The obtained results show that a simple library composed of just three cells - either NAND2, NOR2 and inverters or NAND, NAND3 and inverters - performs very well in terms of transistor count. NAND gates are usually preferred options for ratioed PMOS-only design styles. Using a more complex cell library can produce reductions of around 25% in terms of transistor count, but produce increases of around 23% as well.

Multistandard SoC's including advanced RF and analog circuitry with digital blocks are pervasive in modern IC's. However, the system design and verification methodologies that capture the complexity of multistandard RF SoC's are still limited. In this paper, an HDL design methodology is introduced for multistandard RF SoC's, which covers all the design layers from system design, to automatic extraction of the models from circuits and a systematic top level verification. The offered HDL based design methodology combines top down and bottom up design approaches, and brings the design and verification closer by reflecting the circuits to models automatically via an Automatic Parameter Extraction (APX) tool. System or block level verification is obtained with models automatically by overnight runs, without the need for extra test benches or designer interaction. This enables short term detection of functional errors or performance losses. A first time tape out of a multimode Bluetooth transceiver SoC is designed and fabricated in 8 months by using the offered methodology. The accuracy of the system level simulations show a very good match with the measurement results after fabrication. The test SoC is fabricated with 0.13 μm CMOS technology.

Whereas simulation has long been important in the modeling of ICs, designers have been reluctant to apply it to printed-circuit boards. But an abundance of software is available to speed board design, and it comes without long learning curves or big price tags.

Interconnect delay need not increase as CMOS process geometries shrink, and current IC design methods should suffice for modules of up to 50,000 gates. Beyond that, designers must focus on a new concept - global interconnect design. We consider the effects of both devices and interconnect, and our analysis shows that interconnect delay actually decreases for deep-submicron (DSM) processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs.

International audience