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Antenna-in-Package (AiP) technology has emerged as the mainstream advanced package integrated with antenna and transceiver die for automotive radar application. In this work, thermal performance investigation has been performed on three types of AiP. The effects of underfill material, PCB, RDL, and solder array on package thermal performance has been studied, as well as the combined effects of multiple factors. According to the thermal affecting factors analysis, thermal performance improvement solution has been suggested. All 3 types of package have been analyzed. By using the improvement solution obtained from this analysis, the maximum chip temperature rise can be reduced by ∼20%, and the package internal resistance can be reduced by ∼15%.

Fan-out Wafer Level Packaging (FOWLP) is a versatile semiconductor packaging technology which can be used for various RF and Digital applications. In the FOWLP technology, the bare die IC is embedded in a molding compound for protection, and a Redistribution Layer (RDL) is formed to route the electrical input/output (I/O) of the IC to the solder ball pads which are distributed on the surface area of the package. Besides fanning out of the electrical I/O, it can also be used for multi-chip 2.5D integration. In addition, vertical interconnect can be formed in the molding compound. Together with additional RDL on the top of the package, the FOWLP allows the electrical circuit connection on both sides of the package to form a much compact Package-on-Package or 3D integrated circuit. Furthermore, the RDL can be used to form high performance RF passive circuit to realize an RF System in Package module.

In this paper, a half-bridge leg single phase power package with SiC based MOSFETs (metal-oxide semiconductor field-effect transistors) on a AMB (active metal brazing) substrate was developed. The developed power package consists of a AMB substrate with specially designed cavities, four high power rated SiC chips, three types of customized copper clips forming the source and gate interconnects. High temperature die attach/solder material for the chip, substrate and copper clip bonding, and high temperature endurable encapsulation mould compound (EMC) for cavity and gap filling have been evaluated. The fabricated power packages were undergone the specified reliability assessments, i.e. unbiased highly accelerated stress test (HAST) test, thermal cycling (TC) test (-40~200°C), High temperature storage (HTS) test at 250oC and power cycling test (ΔT=150°C). 5 out of 5 samples passed the standard unbiased HAST test and HTS test for 500 hours. 4 out of 5 samples passed the TC test for 1000 cycles and 3 out of 5 samples passed the power cycling test for 10000 cycles. Electrical open failures were detected between clip 1, traces on the substrate and gate pads of the SiC chips. Interconnects between clip 2/3 and source pads of the SiC chips show good connections. Delamination between the clip 1 and sintered Ag were observed on the failed samples by the cross section failure analysis which is the potential root causes of electrical failure.

TSV-Free Interposer (TFI) has been proposed as a cost-effective package solution alternative to conventional 2.5D package for high-end computing applications. In this study, signal integrity of TFI package is evaluated by both simulation and RF measurements. Well matched RF performance is obtained for both measured and simulated results by using RF test structure fabricated in TFI package. This supports that the TFI interconnects with 6 mm length which is required to connect CPU/GPU and HBM are capable of the data rate of 2 Gbps.

In this work, an aluminum nitride (AlN) based radiofrequency microelectromechanical system (RFMEMS) filter operating at 2.4GHz is characterized on a PCB through wirebonding connection, in order to study the effect of wirebonding on the performance of the filter, in particular the frequency response. Electrical characterization results show that the through proper impedance matching, the bonding wire has minimum effect on the passband and stopband response, e.g., bandwidth, insertion loss, and out-of-band rejection. However, the wirebonding introduces a spurious mode at around 2.37GHz. As a result, the roll-off of the lower edge of the passband gets disturbed. EM simulation will be done to better understand the response of the wirebonding and finally to eliminate the spurious mode.

In this paper, a SiC device based power package with double side cooling capability is designed and developed for high power, high performance application. The developed power package mainly consists of high power rated SiC chips, customized metal clips forming the electrical interconnections, and active metal brazing (AMB) substrates with specially designed cavities. the customized interconnects and the use of paralleled high-power SiC devices in the developed package enable its usage for high power applications. High temperature sustainability is obtained by utilizing the high temperature endurable materials for the interconnections and encapsulation. High thermal performance is realized by shortening the heat transfer path from the SiC chips to liquid cooling heat sink and implementing the double side liquid cooling scheme. In addition, by embedding the chip inside the AMB substrate and replacing the wire-bond interconnections with the flatted copper clip interconnections, the developed power package is with low profile. Significant improvement (> 50%) of the thermal performance has been achieved for the developed power package as compared with the thermal performance of the conventional wire bonded power package. Very low loop inductance along the electric current flow path has been obtained (i.e., 2.7nH at 1Mhz of frequency). High temperature endurable package materials (e.g., die attach and encapsulation material) have been evaluated. The developed power package has been fabricated and passed the specified reliability assessments, i.e., unbiased Highly Accelerated Stress Test (HAST), temperature cycling (TC) test (40 ~200 °C), High temperature storage (HTS) test at 250 °C and power cycling (PC) test ($\Delta$ T= 150 °C).

Two unique multi chips Fan-out Wafer Level Package (FOWLP) designs for High Bandwidth Memory (HBM) integration are illustrated here. HBM is a Wide I/O design and requires very high density routing capability which poses a very challenging electrical design problem for the current FOWLP capability. For both the designs, the signal high speed, high density routing and long interconnect length lead to severe signal distortion and interference issues. In the first design, a silicon chip which consists of all the required high density interface routing fabricated using Back End of Line (BEOL) is embedded inside the FOWLP, this is named as Embedded Fine-Pitch Interposer (EFI). For the other design, the high density routing is achieved by the FOWLP Redistribution Layer (RDL) fine line 2µm width/spacing capability.

TSV-Free Interposer (TFI) packaging technology was developed for central/graphics processing unit (CPU/GPU) and stacked memory system-in-package (SiP) applications. TFI package is targeting to accommodate thick module as High Bandwidth Memory (HBM) and wide-bus interconnections between CPU/GPU and HBM in a package with cost-effective process. The redistribution layer structure was studied based on inter-chip connectivity between CPU/GPU and HBM as well as signal integrity and power integrity. This study demonstrated capability of TFI package in view of electrical performance, cost effectiveness and process challenges. The process challenges were overcome by co-design modeling and process optimizations.

This paper presents the demonstration of integrated passive devices on a 300mm mold-first FOWLP technology platform with 3 metal layers (Cu RDL) build-up. In this case, a low-temperature cure, negative-tone polyimide (PI) material is selected as the inter-layer dielectric. MIM capacitors were fabricated on top of M1 RDL layer with low temperature CVD deposited inorganic as the dielectric and typical RDL barrier metal as the top and bottom electrode. Resistors were formed after M1 RDL layer by using typical RDL barrier metal as the thin film resistor. Last but not least, inductors were built on M2 RDL layer over epoxy mold material. Test keys for MIM capacitors, resistors and inductors were designed for electrical and RF characterization at the M2 layer.

In this paper, a 3-D integrated 77-GHz automotive radar front-end is presented. Embedded wafer level packaging (EMWLP) technology is proposed to eliminate the use of wire bonding, which not only introduces significant radio frequency loss, but also occupies large footprint for high-pin count die. The transceiver bare die is embedded in a reconfigured molded wafer with compression molding process. Double-sided multiple redistribution layers are formed to fan-out the transceiver input/output signals and through mold via is employed to realize the vertical interconnection. With these promising features, the EMWLP technology can be extended to a 3-D integration. A substrate integrated waveguide slot antenna is integrated on top of the EMWLP module and a lens is used to enhance the antenna directivity. The performance of the fully integrated radar front-end is tested and the measurement results show good package performance with RF loss around 5 dB for most of the samples. Temperature cycling reliability test was also performed by letting the fully integrated prototype goes through 1000 temperature cycles with JEDEC standard. The measured package loss spread across samples after 1000 cycles of TC test is about 13 dB, which is mainly due to the antenna warpage affecting the RF path's signal integrity.

In this paper, a 77-GHz automotive radar sensor transceiver front-end module is packaged with a novel embedded wafer level packaging (EMWLP) technology. The bare transceiver die and the pre-fabricated through silicon via (TSV) chip are reconfigured to form a molded wafer through a compression molding process. The TSVs built on a high resistivity wafer serve as vertical interconnects, carrying radio-frequency (RF) signals up to 77 GHz. The RF path transitions are carefully designed to minimize the insertion loss in the frequency band of concern. The proposed EMWLP module also provides a platform to design integrated passive components. A substrate-integrated waveguide resonator is implemented with TSVs as the via fences, and it is later used to design a second-order 77-GHz high performance bandpass filter. Both the resonator and the bandpass filter are fabricated and measured, and the measurement results match with the simulation results very well.

A simple low-cost post-complementary metal-oxide-semiconductor-compatible process to enhance the performance of the planar spiral inductor in standard silicon (Si) substrate is demonstrated. In this process, the high loss and high permittivity of Si which reduces the inductor's performance is replaced by a lower loss and lower permittivity thick polymer material. In this way, a measured high Q-factor of more than 37 and a high self-resonance frequency of 25 GHz are achieved for a 1.7-nH inductor. Using this newly developed process, the performance of the inductor can be further improved by optimizing the design.

In this paper, a 273-GHz 2X subharmonic passive mixer is proposed for system-on-package applications. The mixer is designed and implemented using thin-film microstrip line on a three-layer package platform. The antiparallel-diode-pair-based mixer up-converts the 135-GHz IF input signal to 273 GHz with a 69-GHz local oscillator. The isolation between the IF and RF ports is achieved by a duplexer. The duplexer is composed of two dual-mode bandpass filters with uniform/nonuniform square ring resonators. The mixer is fabricated and measured, and the measured single-sideband conversion loss is 17.7 dB with an output RF of 270 GHz.

This paper presents a terahertz (THz) transmitter (Tx) and receiver (Rx) chipset operating around 400 GHz in 0.13- μm SiGe BiCMOS technology. The Tx chip consists of a voltage-controlled oscillator, a buffer, a modulator, a power amplifier, a frequency tripler, and a substrate integrated waveguide (SIW) antenna. This antenna has an additional high-pass filtering characteristic to suppress the unwanted fundamental (f0) and second harmonic (2f0) signals by 50 and 30 dB, respectively. The Rx chip includes a proposed reconfigurable SIW antenna and a novel two-mode subharmonic mixer with ~ 5-dB reduction of conversion loss. The Rx chip consumes 50 nA from a 1.2-V supply. The measurement results of the Tx and Rx chips and a back-to-back test of the Tx/Rx chipset show the feasibility and pave the way of implementing a fully integrated THz system in silicon technology for mass production.

This paper presents the design, fabrication and “on-wafer” characterization of multi-membrane-supported and polymer-cavity-backed monopole antenna and 2t 1 patch antenna array operating in the 135-GHz frequency range. The designs were fabricated on two-layer benzocyclobutene (BCB) material membrane obtained by micromachining of the low resistivity silicon. The silicon material is removed underneath the monopole antenna to produce a cavity surrounded by metal and filled with polymer. This polymer filled cavity provides a better support to the membrane than conventional air cavity which is extremely important for practical applications. In the meantime, the higher synthesized effective dielectric permittivity of the BCB-polymer mixed region than BCB-air mixed one provides the possibility for compact antenna array designs. The proposed monopole antenna shows a measured impedance bandwidth from 124 to 136 GHz for |S11| less than -10 dB and maximum measured gain of 6.74 dBi at 131 GHz; while the 2t1 patch antenna array achieved a measured impedance bandwidth from 126.5 to 138 GHz for |S11| less than -10 dB and maximum measured gain of 8.66 dBi at 130 GHz.

This paper presents a cavity-backed slot (CBS) antenna for millimeter-wave applications. The cavity of the antenna is fully filled by polymer material. This filling makes the fabrication of a silicon CBS antenna feasible, reduces the cavity size by 76.8%, and also maintains the inherent high-gain and wide bandwidth. In addition, a through-silicon via-based architecture is proposed to integrate the 135-GHz CBS antenna with active circuits for a complete system-in-package. Results show that the proposed structure not only reduces the footprint size but also suppresses the electromagnetic interference.

This paper presents a compact wideband equivalent circuit model for electrical modeling of through-silicon vias (TSVs) in 3-D stacked integrated circuits and packaging. Rigorous closed form formulas for the resistance and inductance of TSVs are de rived from the magneto-quasi-static theory with a Fourier-Bessel expansion approach, whereas analytical formulas from static solutions are used to compute the capacitance and conductance. The equivalent-circuit model can capture the important parasitic effects of TSVs, including the skin effect, proximity effect, lossy effect of silicon, and semiconductor effect. Therefore, it yields accurate results comparable to those with 3-D full-wave solvers.

A low conversion-loss monolithic frequency doubler has been developed for D-band signal generation in 0.13-μm SiGe BiCMOS technology. The circuit uses a single-transistor topology with a novel grounded-shielding structure, which can efficiently reduce the parasitic feedback effect between collector and base of a HBT to achieve frequency multiplication. The measurement results show that the doubler exhibits minimum ~3.2-dB conversion loss at the output frequency of 134 GHz with the efficiency of ~5.8% and maximum -1.4-dBm second-harmonic output power at the output frequency of 132 GHz with the efficiency of ~7%, respectively. Moreover, both input and output return loss are better than 10 dB for the input frequency from 64 to 69 GHz and the corresponding doubled output frequency range. In addition, the estimated rejection of the fundamental signal is better than 20 dB.

The through silicon via (TSV) technology provides a promising option to realize a compact millimeter-wave (mmW) and terahertz (THz) system with high performance. As the fundamental elements in this system, transmission lines (T-lines) and interconnects are very important and therefore studied in this paper. A TSV-based substrate integrated waveguide (SIW) is also characterized. The results show that, the T-lines and interconnects are viable at frequencies lower than ~150 GHz whereas SIW can operate relatively well up to 300 GHz. In addition, two mmW components, i.e., a hairpin filter and a patch antenna, are designed by the TSV technology. Results of all the above passive components indicate that the low-resistivity silicon is the main cause of the total loss. Afterwards, two novel TSV-based topologies are proposed to efficiently integrate an antenna with active circuits for the mmW and THz applications.

With the increasing demand for system integration to cater to continuously increasing number of I/Os as well as higher operating frequencies, reconfigured wafer-level packaging, or embedded WLP (EMWLP) is emerging as a promising technology for integration. This platform allows integrated passives to be designed in the redistribution layers using the mold compound as a substrate, which significantly improves the passives performance compared to those of on-chip. In this paper, we present low loss passives on EMWLP platform demonstrated in a 5.5-GHz band pass filter targeted for wireless local area network (WLAN) applications. To ascertain the feasibility of designing for low loss millimeter wave passives on EMWLP, transmission lines were designed and their loss characteristics investigated up to 110 GHz, which are reported here. Subsequently we demonstrate for the first time a narrowband low loss 77-GHz band pass filter on EMWLP platform, with a good correlation obtained between simulation and measurement results. In addition, a temperature dependence characterization was performed on the 77-GHz filter, with little variation in the measured filter characteristics observed.

Design, measurement, and characterization of a low-loss Lange coupler on Si-substrate up to 170 GHz are presented in this paper. How to determine the value of the even number of the strip lines according to the process design rules is illustrated carefully based on odd- and even-mode impedance theory and calculation. The deembedding procedures of GSG pads and 50 Ω termination resistors are illustrated in details. Simulation and measurement results indicate that the fabricated on-chip 50 Ω resistors can be used for characterization of four-port Lange coupler by two-port network analyzer within expected measurement errors. Measurement results show that the minimum insertion loss of 0.7 dB at central frequency of 140 GHz is achieved, which is in excellent agreement with simulated data.

This paper presents a D-band power amplifler for high- speed communication system. The capacitive efiect of interconnection via on transistor performance at high frequency is analyzed and a new via structure is employed to reduce the capacitive efiect. The on-chip matching technique for high frequency amplifler is analyzed and the thin-fllm microstrip line matching network is used, which is combined with biasing network to reduce RF signal loss and silicon cost. The amplifler is fabricated in 0.13-"m SiGe BiCMOS process. The experimental results show a 7dB gain at 130GHz with 3-dB bandwidth of 30-GHz. The input return loss is better than 10dB over 23GHz. In addition, this amplifler achieves saturated output

An optical subassembly of MUX/DEMUX where optical devices are hybrid-integrated on a silicon optical bench (SiOB) using a passive alignment method is reported. A tight tolerance of positional and tilting angular accuracy is required for optical devices attachment in order to maximize the coupling efficiency. The critical positioning transverse to the optical axis merely depends on the symmetry, and accuracy of the position and shape of trenches. Any inaccuracy primarily affects the noncritical positioning, i.e., z-axis and thetas z, in the direction along the optical axis; misalignment accumulated and causes undesired insertion loss. All the piece parts, i.e., mirror, thin-film filters (TFFs), ball lens, SiOB, etc., have a defined tolerance in their dimensions and surfaces which increases the challenge in achieving high placement accuracy along the optical axis. The effects from these inherent inaccuracies of the position and shape of trenches and piece parts could be minimized by optimizing the adhesive volume, improve the bottom flatness, proper procedure selection. Misalignment at each axis, e.g., x-, y-, z-, thetas x, thetas y, and thetas z was characterized and its effect to the coupling efficiency was discussed.

We report the development of a low cost, simple optical/electrical circuit board (OECB) using multimode polymer waveguide on FR4 printed circuit board (PCB). The design of this OECB uses only a 45deg-ended waveguide to couple and decouple the optical signal directly between the optical devices and the waveguide. The 45deg mirror is formed using excimer laser process on a multimode waveguide with temperature stability at reflow temperature. The optical waveguide is attached to a diced channel in the FR4 PCB using adhesive to form a completely planar circuit. This allows the laser diode and the photodiode to be assembled directly above the input and output of the waveguide using precision flip chip technology, which provides good alignment accuracy. This helps to increase the mechanical reliability of the circuit and minimize assembly requirements. Most importantly, all the electronic and optoelectronic devices used are commercially available components. In the paper, we report the details of the design, simulation result, and the testing results.

This paper presents a down-conversion IQ mixer in 0.13-μm SiGe BiCMOS. The mixer exhibits a measured conversion gain of 1.6 dB at f LO = 135 GHz and P LO = −4.2 dBm. It can directly down-convert 10-Gbps modulated millimeter-wave (mmWave) signals to base-band data. Without any design change or DC bias adjustment, the IQ mixer can operate at any frequency between 77 and 135 GHz. The mixer is therefore universal for many mmWave applications such as 77GHz automotive radars, 94GHz imaging, and 122GHz communications.

The design and analysis of a D-band divide-by-6 injection-locked frequency divider (ILFD) are presented. The circuit employs a microstrip Lange coupler, a microstrip delay line, and a pair of Cascode transistors to form a feedback loop with a center natural frequency of 24GHz to achieve a divide-by-6 frequency division operation. The proposed ILFD is fabricated in a 0.13μm SiGe HBT technology and occupies a silicon arngea of 0.7×0.9mm2. The developed chip shows frequency-division locking range from 135GHz to 150.2GHz with 2dBm input signal while consuming 5.25mW to 14.4mW including the output buffer amplifier. A phase noise of −121.58dBc/Hz at 1MHz offset is achieved at 150.2GHz.

This paper presents a fully-integrated 434GHz transmitter in 0.13μm SiGe BiCMOS. The transmitter consists of a voltage-controlled oscillator, a buffer, a modulator, a power amplifier, a tripler, and an on-chip antenna. The substrate integrated waveguide (SIW) antenna works as an on-chip radiator and a high-pass filter to radiate the desired signal and suppress the unwanted harmonics, respectively. This on-chip antenna has efficiency of 49.8% and antenna gain of −0.55 dBi. The transmitter provides the highest output power of −20 dBm at 434 GHz and shows the potential for near-field active imaging applications.

Wideband directional couplers with high isolation are designed for millimeter-wave applications and implemented in two different in-house Si-based technologies processes — Si-benzocyclobutene (Si-BCB) process and LIGA-like process (lithography, electroplating, and molding). Two 3D tandem directional couplers for millimeter-wave/THz applications have been constructed using the Si-BCB process. The coupling and isolation of tandem coupler have been analyzed from circuit topology. A branch-line coupler is also constructed using the LIGA-like process. The electrical characteristics of these couplers have been simulated in 3D simulator. By comparing the results, the proposed Si-BCB process is noted to provide flexibilities in both the design and implementation of passive components.

In this paper, a through-silicon via (TSV)-based millimeter-wave (mmWave) system-in-package (SiP) is proposed. As a key component in this kind of system, a high-gain wideband antenna is firstly designed using the TSV-compatible Silicon-Benzocyclobutene (Si-BCB) process. By filling the cavity with polymer, the cavity size of the fabricated antenna is reduced by 76.8% comparing with the conventional air cavity. The on-wafer measured 10-dB return loss bandwidth is 110 GHz to 147 GHz. At 135GHz, the antenna gain and the radiation efficiency are up to 6.26 dBi and 86.8%, respectively. These performance parameters are greatly improved compared with those of the conventional on-chip antennas, i.e., about −10 dBi and 10%. Subsequently, rather than the conventional wire-bonding and flip-chip methods, TSV technique is employed to integrate the high-gain antenna with active circuits. The proposed integration architecture not only reduces the footprint of the fully integrated system but also improves the isolation between the designed antenna and active circuits.

A novel Through Silicon Via (TSV) structure to mitigate the high electrical loss at high frequency is presented here. At low frequency, the loss for the TSV is caused mainly by the material loss of the Silicon (Si) substrate due to its low resistivity. However, at millimetre wave (mmWave) frequency range, especially above 50GHz, in addition to the insertion loss, the return loss due to impedance mismatched becomes significant. These losses become a serious setback for the Si Interposer for the mmWave applications. To overcome these losses, polymer cavity formed in the Si substrate with TSV is developed. The polymer has lower loss tangent and lower dielectric constant than Si. These properties can help to reduce the insertion loss and the return loss. Depending on the requirement, multiple set of TSV can be formed on the polymer cavity to provide higher interconnect density. From the simulation results, the new polymer cavity TSV at 100GHz have an insertion loss and return loss of ∼0.2dB and less than −25dB, respectively. On the other hand, conventional high resistivity TSV has an insertion loss and return loss of ∼1.4dB and more than −10dB, respectively, at the same frequency. For higher frequency range, the performance of the polymer cavity TSV is approximately consistent, but the conventional TSV deteriorated drastically. In this paper, the design, fabrication process and the measurement results are presented. The prototype polymer cavity TSV via-line-via test vehicle has a measured insertion loss of less than 1dB and a return loss of better than −10dB through the frequency range up to 110Gz.

At millimeter-wave frequencies, high-gain antenna and its integration with active circuits are of great concern. In this paper, a 2×4 antenna array is designed and fabricated on printed circuit board (PCB). At 135 GHz, the maximum gain is 15.4 dBi. It is much higher than that of a conventional on-chip antenna which is usually lower than −10 dBi. Subsequently, the low-cost wire-bonding technology is studied and adopted to integrate this array with active circuits.

This paper presents the design and characterization of a wideband bandpass filter for millimetre-wave D-band application. The filter is implemented on a three-layer thin film structure using benzocyclobutene (BCB) silicon technology. Two stepped-impedance resonators are used to construct the bandpass filter, while the input/output coupling is achieved by coplanar waveguide (CPW) to stripline transition. The prototype filter is fabricated and measured. The measurement results agree with the simulation results well and exhibit a wideband bandpass filtering response with fractional bandwidth of 32.2% at 135.6 GHz. The mid-band insertion loss is only 2.94 dB.

In this paper, a novel 60 GHz flip-chip bandpass filter in standard CMOS technology is proposed. An insertion loss of 0.69 dB/mm for microstrip line is obtained at 60 GHz by using cascaded THRU de-embedding method. By deploying the gap between the flip-chip bump and the flipped chip, an endcoupled, half-wavelength resonator filter is designed and fabricated. The measured insertion loss of 3.3 dB and return loss of >13 dB with a bandwidth of 63% at centre frequency of 60 GHz clearly demonstrates that the proposed flip-chip filter is a promising candidate for 60 GHz integrated circuits applications.

The design of a true single-phase-clock (TSPC) divider with a division ratio of 8 in 0.13µm BiCMOS technology is presented. Through the careful layout design, the divider is able to operate up to 7.5GHz with the dc voltage supply of 1.8V. The core circuit size is only 80×20µm2.

A 130 GHz low noise amplifier (LNA) in 0.13-μm SiGe BiCMOS technology has been designed and characterized. The gain-boosted cascode topology with 3D grounded-shielding structures is employed. The results showed that the LNA with a chip area of 400 μm × 900 μm, gain of −17.5 dB with a 3-dB bandwidth of −25 GHz, and noise figure of −7.7 dB at 130 GHz with total dc power consumption of 31.5 mW has demonstrated.

This paper presents the design of two types of wideband bandpass filters with different bandwidths for millimeter-wave D-band applications. The proposed filters are implemented on a three-layer structure deposited on a 400-µm silicon (Si) bulk with benzocyclobutene (BCB) as the substrate. The characteristics of the basic structures for these two types of bandpass filters, a square ring resonator and a stub-loaded multiple-mode resonator (MMR), are studied. The bandpass filters are implemented and measured, and the measurement results agree with the simulations well and exhibit bandpass filtering responses at 134.3 GHz and 132.8 GHz, with fractional bandwidths of 25.7% and 34.3%, respectively.

The 3-D integration using through silicon vias (TSVs) is expected to realize compact circuits and systems with high performance and multi-functionality. Based on the TSV technology, a hairpin bandpass filter and a microstrip patch antenna for millimeter-wave (mmW)/terahertz (THz) application are designed and presented in this paper. Additionally, a novel TSV-based solution for the integration of antennas with front-end circuits is proposed. The TSV-based hairpin bandpass filter has the insertion loss of 6.9 dB at 120 GHz with 20 GHz passband from 110 to 130 GHz, whereas the filter size is only 300 × 250 × 50 µm. The designed antenna is with 10-dB impedance bandwidth of 137 to 146 GHz, the boresight directivity and antenna gain is 3.49 dBi and −3.16 dBi, respectively, and the radiation efficiency is 21.6% which is around twice than that of many conventional on-chip antennas. The TSV-based integration solution is expected to reduce not only the total chip size but also the electromagnetic interference (EMI) effect, which are major concerns in the mmW/THz systems.

Transmission lines (T-lines) and interconnects are fundamental components for the millimeter-wave (mmW) and terahertz (THz) circuits. Based on the through-silicon via (TSV) technology, three T-lines, four different interconnects, and one substrate integrated waveguide (SIW) are developed and characterized over a frequency range up to 200 GHz. The results of T-lines show that coplanar waveguide (CPW) is almost with the lowest attenuation whereas microstrip line (MSL) suffers the highest insertion loss. As for the TSV-based interconnects, the 3-D transition from grounded CPW (GCPW) to CPW performs the lowest insertion loss up to 170 GHz. The electromagnetic shock wave is explored to analyze the results and physically explain the related phenomenon. SIW is inherently a good option for the TSV-based THz circuits. However, more research work should be carried out to reduce the high dielectric loss due to the low resistivity of silicon.

With the increasing demand for system integration to cater for continuously increasing I/Os as well as higher operating frequencies, EMWLP is emerging as a promising technology for integration. This platform allows integrated passives to be designed in the redistribution layers using the mold compound as a substrate, which significantly improves the passives performance compared to those of on-chip. In this paper, we present the results of high quality passives on EMWLP platform that are benchmarked against high resistivity silicon (HiRSi). The passives were then demonstrated in two band pass filters targeted to operate in the IEEE 802.11a band, with electrical performances comparable to that of commercial IPDs. Using the same platform, the measured loss characteristics of transmission lines up to 110 GHz is reported. We also demonstrate for the first time a low loss narrowband 77-GHz band pass filter on EMWLP platform, with a good correlation obtained between simulation and measurement results.