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Given the ubiquity of electronic devices and the increasing technical challenges to continue CMOS technology downscaling following Moore's Law, it becomes critical to better quantify the environmental impacts of IC production. In this context, this paper compares 22 key relevant sources, from scientific literature, commercial state-of-the-art databases, industry roadmaps, and foundries CSR reports, over the period 2010–2020. Three environmental indicators, i.e., carbon footprint, primary energy, and water consumption, are considered and normalized per silicon area. Despite a significant variability between the sources, we observe a clear increase of the environmental footprint with technology downscaling. We then use historical data from foundries to analyze the long-term evolution of environmental impacts normalized to the silicon area over 40 years. We highlight the arduous challenge of further decreasing environmental indicators per cm2 below these values. As the global IC production volumes keep on increasing, it raises serious concerns regarding the sustainability of the IC production sub-sector and calls for rethinking the road ahead with sobriety.

Information and communication technologies are often considered by policymakers, industrial stakeholders and scientists as a key lever in the run towards sustainability, since they should ease energy efficiency and dematerialization. In this opinion article, nurtured by the inputs of a broad panel of experts, we challenge this widely spread view by highlighting the detrimental social and environmental footprints caused by digital technologies. We further take a critical look on the ways innovation is conducted nowadays, i.e., with an almost exclusive focus on performance and few considerations for externalities. This leads us to call for academic teaching programs advocating for a holistic approach, for new business models, and for ambitious political decisions able to drive a paradigm shift in the mainstream agenda of electronics innovation and digital transition that shall significantly contribute to the well-being of everyone, everywhere, without compromising future generations. We conclude that digital technologies cannot support long-term sustainability if their only purpose remains the optimization of the current system.

The manufacturing of modern silicon-based MEMS requires highly energy- and resource-intensive processes. Understanding and gathering objective data of the impacts of silicon manufacturing is crucial to select design strategies reducing the environmental impacts. In this work, we present a bottom-up assessment of the embodied energy and carbon footprint of two piezoresistive pressure sensors, by adapting previously published LCA data set to model the sensors process sheets. Then we use these models as generic models of pressure sensors processes to discuss their environmental impacts regarding their performances. Our results highlight that using Silicon-on-Insulator (SOI) substrates and deep reactive ion etching (DRIE) as release process could lead to a 50-fold reduction of the environmental impacts of MEMS pressure sensors regarding to their specifications.

This paper aims at comparing the tuning range of three different planar inductor layouts built on a Printed Circuit Boards (PCB), namely the spiral inductor, the nonspiral inductor, and the meander inductor. Initially, we identify the equivalent electric model for the three inductors. All models are validated theoretically by analytical equations, by simulation through Sonnet software®, and also by measurements. For the same surface occupancy, the spiral inductor presents the higher inductance value, while the nonspiral inductor has the higher quality factor and self-resonant frequency. The tunability range is investigated by placing a shielding metal plate above for all PCB inductors. The inductance value is reduced, when the air gap between the metal plate and the inductance decreases. In addition, results demonstrated that the spiral inductor has the higher range, with a variation of more than 90%, followed by the non-spiral inductor. The meander one showed a change less than one-tenth of the spiral inductor.

We developed a low-cost process for assembling versatile sensors without expensive, thick metal finish on rigid and flexible PCB using anisotropic conductive films (ACF) flip-chip (FC) process. This allows a lower temperature budget than conventional FC assembly. The ACF FC process requires no expensive set up, is quick to implement and suits perfectly for sensor prototyping and low-scale manufacturing. The process was directly applied to assemble the bare die of a CMOS strain gauge sensor on flexible PCB without compromising its integrity.

We present an ultra-thin lateral SOI PIN photodiode with transferred monolayer graphene as the transparent gate, to provide enhanced ultraviolet (UV) performance and mechanical flexibility beyond standard Si-based devices. The device dark current shows intact characteristics after the post-CMOS thinning and graphene transfer processing steps. The device responsivity presents high potential in UV and visible wavelength detections (i.e. within the 200-900 nm range) under monochromatic light illumination. A maximum responsivity of 0.18 A W-1 has been experimentally achieved at 390 nm wavelength and validated by simulation, for a diode with intrinsic length L i of 20 μm. Additionally, the ∼5 μm-thick device chip with direct board assembly paves the way towards the development of hybrid flexible electronics.

In this study, a wireless power transfer system for miniaturized biomedical implants has been optimized for a 1mm-diameter receiver coil. This coil is wire wound around a 7.5 mm-long ferrite core and achieves a 3.56 μH inductance. For a distance of 10 mm between the industrial primary coil and the handmade secondary coil, measurements show a coupling factor of 3% and power transmission efficiencies of 21.6%, 20.8% and 20.5% respectively for a load power consumption of 1 mW, 500 μW and 250 μW, at 1cm distance and at 1 MHz, surpassing previously-reported comparable links.

—In this article, we are presenting a new classification methodology for high resolution membrane based MEMS piezoresistive pressure sensors embedded in Internet of Things (IoT) nodes or in body-implanted devices. This is based on a new figure of merit (FoM) that includes the four key parameters as the power consumption, the area, the noise and the sensitivity of the transducer. The proposed classification allows to directly evaluate, based on power consumption and area requirements, the ultimate limit of detection that can be reached by a proposed technology. The derivation of the proposed FoM is validated based on wide survey and comparisons of literature results. It shows that, until now, wet etching technics for membrane release still allow for reaching higher performances than reactive ion etching.