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Copyright of Atomic Energy Science & Technology is the property of Editorial Board of Atomic Energy Science & Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for computation, utilizing Wafer-on-Wafer (WoW) hybrid bonding and mini Through-Silicon Via (TSV) technologies. This 3DIC architecture includes commercial DRAM, logic, and 3DIC manufacturing processes. Their design documents typically come from different foundries, presenting challenges for signal integrity design and analysis. This paper establishes a lumped circuit based on 3DIC physical structure and calculates all values of the lumped elements in the circuit model with the transmission line model. A Cross-Process Signal Integrity Analysis (CPSIA) method is introduced, which integrates three different manufacturing processes by modeling vertical stacking cells and connecting DRAM and logic netlists in one simulation environment. In combination with the dedicated buffer driving method, the CPSIA method is used to analyze 3DIC impacts. Simulation results show that the timing uncertainty introduced by 3DIC crosstalk ranges from 31 ps to 62 ps. This analysis result explains the stable slight variation in the maximum frequency observed in vertically stacked memory arrays from different DRAM layers in the physical testing results, demonstrating the effectiveness of this CPSIA method. [ABSTRACT FROM AUTHOR]

In implantable electrophysiological recording systems, the headstage typically comprises neural probes that interface with brain tissue and integrated circuit chips for signal processing. While advancements in MEMS and CMOS technology have significantly improved these components, their interconnection still relies on conventional printed circuit boards and sophisticated adapters. This conventional approach adds considerable weight and volume to the package, especially for high channel count systems. To address this issue, we developed a through-polymer via (TPV) method inspired by the through-silicon via (TSV) technique in advanced three-dimensional packaging. This innovation enables the vertical integration of flexible probes, amplifier chips, and PCBs, realizing a flexible, lightweight, and integrated device (FLID). The total weight of the FLIDis only 25% that of its conventional counterparts relying on adapters, which significantly increased the activity levels of animals wearing the FLIDs to nearly match the levels of control animals without implants. Furthermore, by incorporating a platinum-iridium alloy as the top layer material for electrical contact, the FLID realizes exceptional electrical performance, enabling in vivo measurements of both local field potentials and individual neuron action potentials. These findings showcase the potential of FLIDs in scaling up implantable neural recording systems and mark a significant advancement in the field of neurotechnology. [ABSTRACT FROM AUTHOR]

Recent development in heterogeneous integration for high-performance chips (HPC) demands higher power, which induces a higher level of current density per through-silicon via (TSV) and redistribution layer (RDL) interconnects. Change in electrical and thermomechanical properties during long-term current stressing can result in negative impact on signal integrity and reliability of the device. In this study, test samples of Si interposers containing TSVs with a multilayered RDL structure at the top were tested under current densities ranging from 1 × 105 A/cm2 to 2.5 × 105 A/cm2 at 200°C in vacuum. Microstructural changes were observed in the current-carrying TSVs, and the circuit resistance increased sharply during the test. This increase was associated with several damage modes, including migration of Sn and Ag from solder, and Ni from under-bump metallization, driven by electromigration, leading to alloying and formation of reaction products. A volume increase associated with phase transformations and electromigration-induced void formation defects are identified under highly accelerated testing conditions, which potentially affect the long-term reliability of TSV-containing structures and need to be considered in design and manufacturing protocols for devices and packages. [ABSTRACT FROM AUTHOR]

This document is an editorial for a special issue of the journal Micromachines on the topic of state-of-the-art CMOS and MEMS devices. The editorial highlights the importance of CMOS and MEMS devices in emerging research fields such as artificial intelligence, 5G communication, the Internet of Things, and satellite communication. It mentions that the research in this field is focused on design, modeling, fabrication, and application of CMOS and MEMS devices. The special issue contains 10 published articles that address the demand for high-performance silicon ICs and MEMS devices and explore device and circuit design techniques, performance optimization methods, and system integration strategies. The editorial concludes by acknowledging the challenges and obstacles that remain in the field and expressing hope that the articles in the special issue will be interesting and inspiring for readers. [Extracted from the article]

A meta-surface-based arbitrary bandwidth filter realization method for terahertz (THz) future communications is presented. The approach involves integrating a meta-surface-based bandstop filter into an ultra-wideband (UWB) bandpass filter and adjusting the operating frequency range of the meta-surface bandstop filter to realize the design of arbitrary bandwidth filters. It effectively addresses the complexity of designing traditional arbitrary bandwidth filters and the challenges in achieving impedance matching. To underscore its practicality, the paper employs silicon substrate integrated gap waveguide (SSIGW) and this method to craft a THz filter. To begin, design equations for electromagnetic band gap (EBG) structures were developed in accordance with the requirements of through-silicon via (TSV) and applied to the design of the SSIGW. Subsequently, this article employs equivalent transmission line models and equivalent circuits to conduct theoretical analyses for both the UWB passband and the meta-surface stopband portions. The proposed THz filter boasts a center frequency of 0.151 THz, a relative bandwidth of 6.9%, insertion loss below 0.68 dB, and stopbands exceeding 20 GHz in both upper and lower ranges. The in-band group delay is 0.119 ± 0.048 ns. Compared to reported THz filters, the SSIGW filter boasts advantages such as low loss and minimal delay, making it even more suitable for future wireless communication. [ABSTRACT FROM AUTHOR]

This document is an editorial for a special issue of the journal Micromachines focused on advanced interconnect and packaging technologies in the field of electronics. The editorial highlights the importance of these technologies in achieving high performance, miniaturization, and low power consumption in electronic devices. It introduces several research contributions included in the special issue, covering topics such as built-in packaging methods, bonding strength improvement, accurate characterization of interconnects, signal and power integrity analyses, crosstalk reduction, and reliability issues. The editorial acknowledges the challenges that remain in this field and expresses gratitude to the authors, editors, and reviewers involved in the special issue. [Extracted from the article]

The main challenges in 3D metrology involve measuring TSVs etched with very high aspect ratios, where the via depth to diameter ratio approaches 10:1–20:1. In this paper, we introduce an innovative approach to enhance our in-house spectroscopic reflectometer module by integrating aperture technology, resulting in a substantial amplification of interference signals. Our system offers the flexibility to conduct measurements on an average number of TSVs, individual TSVs, or specific periodic arrays of TSVs. Additionally, we demonstrate the utility of the spectroscopic reflectometer as a non-destructive, high-speed metrology solution for in-line monitoring of TSV etch uniformity. Through a series of experimental trials in a reactive ion etch (RIE) process, we show that leveraging feedback data from the reflectometer leads to marked improvements in etch depth uniformity.

Copyright of Electroplating & Finishing is the property of Electroplating & Finishing Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The main challenges in 3D metrology involve measuring TSVs etched with very high aspect ratios, where the via depth to diameter ratio approaches 10:1–20:1. In this paper, we introduce an innovative approach to enhance our in-house spectroscopic reflectometer module by integrating aperture technology, resulting in a substantial amplification of interference signals. Our system offers the flexibility to conduct measurements on an average number of TSVs, individual TSVs, or specific periodic arrays of TSVs. Additionally, we demonstrate the utility of the spectroscopic reflectometer as a non-destructive, high-speed metrology solution for in-line monitoring of TSV etch uniformity. Through a series of experimental trials in a reactive ion etch (RIE) process, we show that leveraging feedback data from the reflectometer leads to marked improvements in etch depth uniformity. [ABSTRACT FROM AUTHOR]

In this article, we propose a fast three‐dimensional integrated circuit (3D‐IC) floorplanning method for hard macroblocks that includes a thermal management scheme. It applies a genetic algorithm constituted by an optimal combination of crossover and mutation operations to identify the optimal solution for design variables, namely, total wire length, number of through‐silicon vias (TSVs), and maximum average layer power density. The proposed method additionally makes use of a unique TSV placement scheme that arranges TSVs next to their respective functional blocks. To enable efficient heat transmission to the ambient environment, layers with higher power densities are placed closer to the heat sink. The proposed 3D‐IC floorplanning approach provides the fewest TSVs, the lowest peak temperature, and promising values of wire length within the least amount of computation time. Compared to the recent fast thermal analysis for fixed‐outline 3D‐floorplanning, it generates 13.14% shorter wire length, 39.27% lower peak temperature, and 34.35% lesser number of TSVs on average with significant improvement in computation time, while analyzing GSRC thermal benchmark circuits. [ABSTRACT FROM AUTHOR]

This review investigates the measurement methods employed to assess the geometry and electrical properties of through-silicon vias (TSVs) and examines the reliability issues associated with TSVs in 3D integrated circuits (ICs). Presently, measurements of TSVs primarily focus on their geometry, filling defects, and the integrity of the insulating dielectric liner. Non-destructive measurement techniques for TSV contours and copper fillings have emerged as a significant area of research. This review discusses the non-destructive measurement of contours using high-frequency signal analysis methods, which aid in determining the stress distribution and reliability risks of TSVs. Additionally, a non-destructive thermal detection method is presented for identifying copper fillings in TSVs. This method exploits the distinct external characteristics exhibited by intact and defective TSVs under thermoelectric coupling excitation. The reliability risks associated with TSVs in service primarily arise from copper contamination, thermal fields in 3D-ICs, stress fields, noise coupling between TSVs, and the interactions among multiple physical fields. These reliability risks impose stringent requirements on the design of 3D-ICs featuring TSVs. It is necessary to electrically characterize the influence of copper contamination resulting from the TSV filling process on the reliability of 3D-ICs over time. Furthermore, the assessment of stress distribution in TSVs necessitates a combination of micro-Raman spectroscopy and finite element simulations. To mitigate cross-coupling effects between TSVs, the insertion of a shield between them is proposed. For efficient optimization of shield placement at the chip level, the geometric model of TSV cross-coupling requires continuous refinement for finite element calculations. Numerical simulations based on finite element methods, artificial intelligence, and machine learning have been applied in this field. Nonetheless, comprehensive design tools and methods in this domain are still lacking. Moreover, the increasing integration of 3D-ICs poses challenges to the manufacturing process of TSVs. [ABSTRACT FROM AUTHOR]

Following Moore's law, the density of integrated circuits is increasing in all dimensions, for instance, in 3D stacked chip networks. Amongst other electro-optic solutions, multimode optical interconnects on a silicon interposer promise to enable high throughput for modern hardware platforms in a restricted space. Such integrated architectures require confidential communication between multiple chips as a key factor for high-performance infrastructures in the 5G era and beyond. Physical layer security is an approach providing information theoretic security among network participants, exploiting the uniqueness of the data channel. We experimentally project orthogonal and non-orthogonal symbols through 380 μ m long multimode on-chip interconnects by wavefront shaping. These interconnects are investigated for their uniqueness by repeating these experiments across multiple channels and samples. We show that the detected speckle patterns resulting from modal crosstalk can be recognized by training a deep neural network, which is used to transform these patterns into a corresponding readable output. The results showcase the feasibility of applying physical layer security to multimode interconnects on silicon interposers for confidential optical 3D chip networks. [ABSTRACT FROM AUTHOR]

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed. [ABSTRACT FROM AUTHOR]

Considering the manufacturing and packaging process, 3-D integrated circuits design often requires irregular chip structures. The 3-D integrated circuits with irregular structures can facilitate differentiated chip design and reduce manufacturing costs. Highly complex through-silicon vias have not been considered in past thermal modelling and analysis of irregularly structured 3-D integrated circuits. Thus, a detailed model of a three-layer irregularly structured 3-D integrated circuit with through-silicon vias and microbumps is developed, and an analytical method based on the thermal resistance network model is proposed to extract the equivalent thermal conductivity of through-silicon vias and microbumps, the accuracy of which is verified by a 3-D finite element simulation method. The results show that the maximum temperature and temperature gradient obtained by the equivalent model simulations agree well with the detailed model results, proving the validity of the equivalent model. To save the computational cost, the effects of heat source area, power setting and through-silicon vias structure parameters on the maximum temperature are studied by numerical simulation method based on the equivalent model. Heat source area equal to the overlap between chip layers, high power chips close to the heat sink, and reducing through-silicon vias pitch can better reduce the maximum temperature. The results provide a reference value for thermal design and optimization of 3-D integrated circuits with irregular structures. [ABSTRACT FROM AUTHOR]

Radio frequency (RF) systems utilizing through-silicon vias (TSVs) have been widely used in the aerospace and nuclear industry, which means that studying the total ionizing dose (TID) effect on TSV structures has become necessary. To investigate the TID effect on TSV structures, a 1D TSV capacitance model was established in COMSOL Multiphysics (COMSOL), and the impact of irradiation was simulated. Then, three types of TSV components were designed, and an irradiation experiment based on them was conducted, to validate the simulation results. After irradiation, the S21 degraded for 0.2 dB, 0.6 dB, and 0.8 dB, at the irradiation dose of 30 krad (Si), 90 krad (Si), 150 krad (Si), respectively. The variation trend was consistent with the simulation in the high-frequency structure simulator (HFSS), and the effect of irradiation on the TSV component was nonlinear. With the increase in the irradiation dose, the S21 of TSV components deteriorated, while the variation of S21 decreased. The simulation and irradiation experiment validated a relatively accurate method for assessing the RF systems' performance under an irradiation environment, and the TID effect on structures similar to TSVs in RF systems, such as through-silicon capacitors. [ABSTRACT FROM AUTHOR]

The Cu-filling process in through-silicon via (TSV-Cu) is a key technology for chip stacking and three-dimensional vertical packaging. During this process, defects resulting from chemical–mechanical planarization (CMP) and annealing severely affect the reliability of the chips. Traditional methods of defect characterization are destructive and cumbersome. In this study, a new defect inspection method was developed using Mueller matrix spectroscopic ellipsometry. TSV-Cu with a 3-μm-diameter and 8-μm-deep Cu filling showed three typical types of characteristics: overdishing (defect-OD), protrusion (defect-P), and defect-free. The process dimension for each defect was 13 nm. First, the three typical defects caused by CMP and annealing were investigated. With single-channel deep learning and a Mueller matrix element (MME), the TSV-Cu defect types could be distinguished with an accuracy rate of 99.94%. Next, seven effective MMEs were used as independent channels in the artificial neural network to quantify the height variation in the Cu filling in the z-direction. The accuracy rate was 98.92% after training, and the recognition accuracy reached 1 nm. The proposed approach rapidly and nondestructively evaluates the annealing bonding performance of CMP processes, which can improve the reliability of high-density integration. [ABSTRACT FROM AUTHOR]

Through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit (3-D IC), which can transfer heat from multiple dies to the heat sink in vertical direction. In this paper, a new general model of the through-silicon via (TSV) is proposed to investigate the thermal performance of the 3-D IC. The heat transfer characteristics of conical-annular TSV are studied for the first time. The impacts of different sidewall inclination angles and insulating layer thicknesses of TSV on the heat dissipation of 3-D IC were compared and analyzed in detail. As expected, our proposed model is in good agreement with the results of the existing models, which shows that the proposed model considering the lateral heat transfer and TSV structures can predict the distribution of temperature more efficiently and accurately. Furthermore, it is found that conical-annular TSV has more excellent heat dissipation performance. [ABSTRACT FROM AUTHOR]

Purpose: Bumpless Cu/SiO2 hybrid bonding, which this paper aims to, is a key technology of three-dimensional (3D) high-density integration to promote the integrated circuits industry's continuous development, which achieves the stacks of chips vertically connected via through-silicon via. Surface-activated bonding (SAB) and thermal-compression bonding (TCB) are used, but both have some shortcomings. The SAB method is overdemanding in the bonding environment, and the TCB method requires a high temperature to remove copper oxide from surfaces, which increases the thermal budget and grossly damages the fine-pitch device. Design/methodology/approach: In this review, methods to prevent and remove copper oxidation in the whole bonding process for a lower bonding temperature, such as wet treatment, plasma surface activation, nanotwinned copper and the metal passivation layer, are investigated. Findings: The cooperative bonding method combining wet treatment and plasma activation shows outstanding technological superiority without the high cost and additional necessity of copper passivation in manufacture. Cu/SiO2 hybrid bonding has great potential to effectively enhance the integration density in future 3D packaging for artificial intelligence, the internet of things and other high-density chips. Originality/value: To achieve heterogeneous bonding at a lower temperature, the SAB method, chemical treatment and the plasma-assisted bonding method (based on TCB) are used, and surface-enhanced measurements such as nanotwinned copper and the metal passivation layer are also applied to prevent surface copper oxide. [ABSTRACT FROM AUTHOR]

Packaging is a pivotal step in electronic device manufacturing, determining the translational performance of bare chips. In summary, although emerging technologies might be quite different when electronic devices turn "soft", the essence of electronic packaging technology will always focus on the interconnection, integration, and protection of associated microsystems. More broadly, for the development of mainstream "Hard" packaging technology, that is, "More Moore" or "More-than-Moore", gives us opportunities to explore the unknown with non-generic packaging designs for integrated circuit (IC), micro-electro-mechanical system (MEMS), optoelectronics, lasing photonics, and power electronics, among others. Currently, the total number of micro-bumps in a single advanced integrated circuit (IC) chip has already surpassed 100,000, and the pitch size between adjacent microbumps can be lower than 20 m. Therefore, the continuing pursuit of bonding technology [[5]] is driven by the down-scaling trend of microbumps with an ultra-fine pitch for a more compact and reliable design of 3D packaging architectures. [Extracted from the article]

An efficient multi-objective optimization method of temperature and stress for a microsystem based on particle swarm optimization (PSO) was established, which is used to map the relationship between through-silicon via (TSV) structural design parameters and performance objectives in the microsystem, and complete optimization temperature, stress and thermal expansion deformation efficiently. The relationship between the design and performance parameters is obtained by a finite element method (FEM) simulation model. The neural network is built and trained in order to understand the mapping relationship. Then, the design parameters are iteratively optimized using the PSO algorithm, and the FEM results are used to verify the efficiency and reliability of the optimization methods. When the optimization target of peak temperature, bump temperature, TSV temperature, maximum stress and maximum thermal deformation are set as 100 °C, 55 °C, 35 °C, 180 Mpa and 12 μm, the optimization results are as follows: the peak temperature is 97.90 °C, the bump temperature is 56.01 °C, the TSV temperature is 31.52 °C, the maximum stress is 247.4 Mpa and the maximum expansion deformation is 11.14 μm. The corresponding TSV structure design parameters are as follows: the radius of TSV is 10.28 μm, the pitch is 65 μm and the thickness of SiO2 is 0.83 μm. The error between the optimization result and the target temperature is 2.1%, 1.8%, 9.9%, 37.4% and 7.2% respectively. The PSO method has been verified by regression analysis, and the difference between the temperature and deformation optimization results of the FEM method is not more than 3%. The stress error has been analyzed, and the reliability of the developed method has been verified. While ensuring the accuracy of the results, the proposed optimization method reduces the time consumption of a single simulation from 2 h to 70 s, saves a lot of time and human resources, greatly improves the efficiency of the optimization design of microsystems, and has great significance for the development of microsystems. [ABSTRACT FROM AUTHOR]

In this study, an ultra-high-resolution acoustic microscopy system capable of non-destructively evaluating defects that may occur in thin film structures was fabricated. It is an integrated system of the control module, activation module, and data acquisition system, in which an integrated control software for controlling each module was developed. The control module includes the mechanical, control, and ultrasonic parts. The activation module was composed of the pulser/receiver, and the data acquisition system included an A/D board. In addition, the integrated control software performs system operation and material measurement and includes an analysis program to analyze the obtained A-Scan signals in various ways. A through-silicon via (TSV) device, which is a semiconductor structure, was prepared to verify the performance of the developed system. The TSV device was analyzed using an ultra-high-resolution acoustic microscope. When the C-Scan images were analyzed, void defects with a size of 20 μm were detected at a depth of approximately 32.5 μm. A similar result could be confirmed when the cross section was measured using focused ion beam (FIB) microscopy. [ABSTRACT FROM AUTHOR]

In order to obtain high-quality through-silicon via (TSV) arrays for high voltage applications, we optimized the fabrication processes of the Si holes, evaluated the dielectric layers, carried out hole filling by Cu plating, and detected the final structure and electric properties of the TSVs. The Si through-hole array was fabricated in an 8-inch Si substrate as follows: First, a blind Si hole array was formed by the Si deep reactive etching (DRIE) technique using the Bosch process, but with the largest width of the top scallops reduced to 540 nm and the largest notch elimidiameternated by backside grinding, which also opens the bottom ends of the Si blind holes and forms 500-μm-deep Si through holes. Then, the sidewalls of the Si holes were further smoothed by a combination of thermal oxidation and wet etching of the thermal oxide. The insulating capability of the dielectric layers was evaluated prior to metal filling by using a test kit. The metal filling of the through holes was carried out by bottom-up Cu electroplating and followed by annealing at 300 °C for 1 h to release the electroplating stress and to prevent possible large metal thermal expansion in subsequent high-temperature processes. The TSV arrays with different hole diameters and spacing were detected: no visible defects or structure peeling was found by scanning electron microscopy (SEM) observations, and no detectable interdiffusion between Cu and the dielectric layers was detected by energy dispersive X-ray (EDX) analyses. Electric tests indicated that the leakage currents between two adjacent TSVs were as low as 6.80 × 10−10 A when a DC voltage was ramped up from 0 to 350 V, and 2.86 × 10−9 A after a DC voltage was kept at 100 V for 200 s. [ABSTRACT FROM AUTHOR]

The development of radio-frequency integrated circuits (RF-IC) necessitates higher requirements for the size of microtransformers. This paper describes millimeter-scale 3D transformers in millimeter-scale, solenoidal, and toroidal transformers manufactured using Micro-electromechanical Systems (MEMS). Two through-silicon via (TSV) copper coils with a high aspect ratio are precisely interleaved on a reserved air core (magnet core cavity) with a vertical height of over 1 mm because of the thickness of the substrate, which increases the performance while reducing the footprint. The effects of the wire width, coil turns, magnetic core, and substrate on the performance of the two transformers are discussed through numerical simulations. When an air core is present, solenoidal transformers are better than toroidal transformers in terms of performance and footprint; however, the gap decreases when the size is reduced. Additionally, the magnetic core significantly improves the performance of the toroidal transformer compared to that of the solenoid. Thus, the toroidal transformer has a higher potential for further size reduction. The two types of transformers were then manufactured completely using MEMS and electroplating. This paper discusses the influence of various parameters on millimeter-scale 3D transformers and realizes processing in silicon, which provides the foundation for integrating transformers in a chip. [ABSTRACT FROM AUTHOR]

High-bandwidth memory (HBM) offers breakthrough memory bandwidth through its vertically stacked memory architecture and through-silicon via (TSV)-based fast interconnect. However, the stacked architecture leads to high-power density causing thermal issues when running modern memory-hungry workloads such as deep neural networks (DNNs). Prior works on dynamic thermal management (DTM) of 3-D DRAM do not consider the physical structure of HBM and often lead to heavy DTM-induced performance penalty. We propose an application-aware efficient task mapping and migration-based DTM policy that maps DNN instances to cores through exploiting the channel layout of HBM and leveraging the significant temperature gradient across DRAM dies while making thermal decisions. We utilize the variation in the memory access behavior of DNN layers and attempt to minimize stalling due to thermal hotspots in the HBM stack. We also use application-aware dynamic voltage and frequency scaling (DVFS) and DRAM low-power states to further improve performance. Experimental results on workloads comprising seven popular DNNs show that NeuroMap results in an average execution time and memory energy reduction of 39% and 40%, respectively, over state-of-the-art DTM mechanisms. [ABSTRACT FROM AUTHOR]

In this work, we present a thin-profile, efficient power delivery approach, including a voltage regulator with in-package power inductor and backside power delivery network (PDN). To meet 1- $\mathrm {W}/{\mathrm {mm}}^{2}$ power-density target for high-performance computing (HPC) systems, a 25-high- $Q$ -factor (300 MHz), 150- $\mu \text{m}$ -thick, in-molding power inductor is provided for high-efficiency point-of-load (PoL) voltage regulation. Meanwhile, a novel analytical model for backside power delivery is developed for computer-aided-design (CAD) procedure to optimize the system efficiency. For the power flowing from bumps (57- $\mu \text{m} V_{\mathrm {DD}}$ -bump pitch) and backside PDN to active devices, the area resistances contributed by backside PDN and the buried power rail (BPR) are 23% and 77%, respectively, if a 10- $\mu \text{m}$ -horizontal-pitch nano- through-silicon via ($n$ TSV) is available. The resulting impact on power dissipation is within 1% so negligible. A higher ratio (0.5) buck converter with maintained efficiency is combined to better benefit the external interconnect. The overall power delivery efficiency $\eta \,\,=83$ % can be obtained for 1- $\mathrm {W}/{\mathrm {mm}}^{2}$ power-density target. The power losses contributed by an air-core inductor, power switches, and PDN/BPR/redistribution layer (RDL) are 26%, 66%, and 8%, respectively. [ABSTRACT FROM AUTHOR]

In 2.5/3D(2.5/3-dimensional) packages, TSV (Through-Silicon Via) technology is crucial for achieving high performance and low power consumption. However, there are still challenges when it comes to uniformly filling TSVs on 300 mm whole wafers without defects. This study focuses on addressing this issue by designing a rotating cathode carrier with a 300 mm diameter, simulating the plating environment in different areas of a 300 mm wafer. The effects of plating conditions, such as cathode rotational speed and chip mounting position, on the filling of TSV are investigated. The TSV have a hole diameter of 10 μm and a depth of 100 μm.The findings reveal that when the cathode carrier rotates at a speed of 30 rpm, different areas of the analog wafer exhibit complete filling of TSV. Additionally, a surface plating layer with an average thickness of approximately 3 μm is obtained. [Display omitted] • A new wafer-level TSV plating device was designed to study the copper plating and filling process of wafer-level TSVs. • In the study of wafer-level TSV plating and filling, a rotating cathode was designed and a flow field was introduced to improve the plating effect. • Simulation of flow field and concentration field for wafer-level plating device was instructed [ABSTRACT FROM AUTHOR]

This paper presents an in- depth investigation of the silicon substrate characteristics based on frequency-dependent parameters in the through-silicon via (TSV)-based 3-D ICs. It is the first time to define the frequency bands accurately on the ground of a quantitative standard of calibration to represent different characteristics of the silicon substrate. Moreover, by converting the conventional model of a TSV pair into an RC parallel circuit, a simplified model is established which makes the analysis of the silicon substrate concise associated with the frequency variation. To further reveal the influence of silicon substrate on the signal transmission between adjacent TSVs, relevant impedance parameters of the silicon substrate are converted into the impedance ( $Z$ ) matrix for parametric modeling, which is validated by 3D full-wave simulations. This work contributes a systematic examination of the silicon substrate characteristics with the variation of frequency, and provides significant guidance for parametric analysis and modeling in TSV-based 3-D ICs.

A high-density symmetrical transformer based on through-silicon via (TSV) is proposed in this article. The primary winding and secondary winding have strong symmetry, and the inductance mismatch is less than 0.1%, so the transformer structure is suitable for differential circuit. Compared with transformers in other literatures, the proposed transformer has advantages in area and efficiency, which is reflected in that the on-chip area is greatly reduced by 58% to 89%, and the coupling coefficient can reach more than 0.92. [ABSTRACT FROM AUTHOR]

Planar MOS/MEMS gas sensors have been widely studied and applied, but the detection of exhaled gas has been little developed. The flow rate of exhaled gas affects the suspension structure of the MEMS gas sensor and the operating temperature of the gas sensor. Therefore, this study uses the Bosch process and the atomic layer deposition (ALD) process to prepare a room-temperature (RT) TSV-structured TiO2 gas sensor. The results indicated that the TiO2 sensing film is uniformed and covers the through-silicon via (TSV) structure and the TiO2 sensing film is confirmed to be a p-type MOS. In terms of gas sensing at room temperature, the response of the sensor increases with the increasing NO concentration. The sensor response is 16.5% on average, with an inaccuracy of <± 0.5% for five cycles at 4 ppm NO concentration. For gas at 10 ppm, the response of the sensor to NO is 24.4%, but the sensor produces almost no response to other gases (CO, CO2, SO2, and H2S). The RT TiO2 gas sensor with a TSV structure exhibits good stability, reversibility, and selectivity to NO gas. [ABSTRACT FROM AUTHOR]

A switchable bandstop filter (BSF) bank in 3-D heterogeneous integration is presented in this article for multiband applications. Compared with conventional filter banks, the proposed design features wide bandwidth, sharp skirts, compact size, and high integration. In the proposed BSF, double short-ended coupling lines are introduced to expand the operation bandwidth with sharp rejection. Moreover, to significantly reduce the size of the proposed BSFs, an in-house silicon micromachining process is developed to heterogeneously integrate two stacked BSFs with switches by through-silicon vias (TSVs). To experimentally validate the proposed configuration, a two-channel switchable BSF bank is designed, fabricated, and measured. The measured results show a tuning range of 7.95–12.3 GHz (43%), a maximum bandwidth of 30%, and a sharp stopband rejection of 50 dB. These results agree well with simulation. Moreover, the fabricated prototype is only 15 $\times 8\times $ 1 mm3, whereas a typical industrial counterpart is around $86\times 74\times18$ mm3, i.e., the size is significantly reduced to 1‱. To the best of the authors’ knowledge, this is the first demonstration of a wideband switchable sharp-rejection BSF chip fully integrated in the TSV process. [ABSTRACT FROM AUTHOR]

A miniature integrable transformer is an obstacle to the miniaturization of packaged power supply on chip (PwrSoC). This letter introduces a through-silicon via (TSV) high-aspect-ratio toroidal transformer manufactured using microelectro-mechanical systems and electroplating. The primary coil and secondary coil of the transformer are interleaved on the toroidal core cavity, which is entirely wrapped in silicon, and a 1.2 mm high toroidal Ni-Zn ferrite core is formed. A 15:15 turn transformer is fabricated with a compact coil size of Φ4.1 × 2 mm with an aspect ratio (ratio of TSV depth to diameter) of 20. Measurements show that it has an inductance of 105 to 115 nH in a high frequency range of 1 to 80 MHz and a coupling coefficient of ∼0.7 in the range of 1 MHz to >15 MHz. Compared to that of the transformer without the Ni-Zn ferrite core, the coupling coefficient of the toroidal transformer increases by 40% with an inductance increase of 20%. At a frequency of 14 MHz, the transformer has a maximum quality factor of 16.7. The small size, IC compatible manufacturing process and excellent performance at high-frequency of the transformer proposed, meet the further integrated and miniaturized needs of PwrSoC. [ABSTRACT FROM AUTHOR]

Since the three-dimensional Network on Chip (3D NoC) uses through-silicon via technology to connect the chips, each silicon layer is conducted through heterogeneous thermal, and 3D NoC system suffers from thermal problems. To alleviate the seriousness of the thermal problem, the distribution of data packets usually relies on traffic information or historical temperature information. However, thermal problems in 3D NoC cannot be solved only based on traffic or temperature information. Therefore, we propose a Score-Based Traffic- and Thermal-Aware Adaptive Routing (STTAR) that applies traffic load and temperature information to routing. First, the STTAR dynamically adjusts the input and output buffer lengths of each router with traffic load information to limit routing resources in overheated areas and control the rate of temperature rise. Second, STTAR adopts a scoring strategy based on temperature and the number of free slots in the buffer to avoid data packets being transmitted to high-temperature areas and congested areas and to improve the rationality of selecting routing output nodes. In our experiments, the proposed scoring Score-Based Traffic- and Thermal-Aware Adaptive Routing (STTAR) scheme can increase the throughput by about 14.98% to 47.90% and reduce the delay by about 10.80% to 35.36% compared with the previous works. [ABSTRACT FROM AUTHOR]

This article is devoted to the synergistic design of the thermal management and signal integrity for 3-D integrated chips. The structure parameters of the micro-fin and interconnected components are optimized to obtain a balanced performance of chip heat dissipation and signal integrity. The 3-D integrated chip flows heat transfer model under the action of electrothermal coupling is developed. A full-wave electromagnetic simulation model of the signal interconnection components is proposed with the same structural parameters. The effects of various structural factors on the heat transfer performance and signal integrity of 3-D integrated chips are investigated. A multiobjective optimization algorithm is carried out to simultaneously reduce the total thermal resistance of the 3-D integrated chip and the signal transmission losses of the critical interconnect components. The results show that the total thermal resistance of the 3-D IC becomes lower with a larger through-silicon via (TSV) diameter, micro-fins height and micro-fin radius, and smaller oxide thickness. When the TSV diameter and oxide thickness increase, the height and radius of the micro-fins are reduced to facilitate the signal transmission of the chip’s interconnected components. The response surface analysis method was used to design the experimental combination and thus obtain the fit function for the performance of the two objectives. Hundred sets of Pareto optimal solutions are obtained by multiobjective optimization. The technique for order preference by similarity to ideal solution (TOPSIS) method is used to select the weights of the two optimization objectives to determine the optimal solution. When thermal resistance and signal transmission are given equal weight in the chip design, thermal resistance is reduced by 13.8%, and signal transmission efficiency is improved by 9.74%. The study has important implications for chip thermal management and signal integrity. [ABSTRACT FROM AUTHOR]

In this study, the recent advances and trends in multiple system and heterogeneous integration with through-silicon via (TSV)-less interposer (organic interposer or 2.3-D IC integration) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV-less interposer. Also, some recommendations of 2.3-D IC integration will be provided. [ABSTRACT FROM AUTHOR]

An original concept of 3-D through-silicon via (TSV)-based Marchand baluns and its design methodology is proposed for on- chip and 3-D integration. By utilizing a 3-D packaging process that includes a TSV and redistribution layer (RDL), a meander coupling path is established and embedded in the vertical direction of the substrate for balun design. The 3-D structure can effectively reduce the on- chip area while maintaining good balance characteristics. Furthermore, the structure can be flexibly integrated with 3-D integrated circuits (3-D ICs) to realize signal conversion between different stacking tiers. An equivalent circuit model based on the TSV-to-TSV coupling channel and coupled transmission line has been established for initial estimation before electromagnetic (EM) optimization. To shorten the design cycle, a specific flow is proposed to meet the structural particularity and different application scenarios. To verify the design method and flow, a design case is analyzed and EM simulated with the antenna feeding network as the target application. The EM simulation results show that the design can work at 43–82 GHz with an amplitude imbalance of less than 0.3 dB and a phase imbalance of less than 1.3°, which meets the requirements of balanced feeding. It only costs a $0.084\,\,\lambda _{\text {g}}\,{\times }\,0.009\,\,\lambda _{\text {g}}$ footprint, which is far lower than that of the conventional planar types. [ABSTRACT FROM AUTHOR]

Following Moore’s law, the density of integrated circuits is increasing in all dimensions, for instance, in 3D stacked chip networks. Amongst other electro-optic solutions, multimode optical interconnects on a silicon interposer promise to enable high throughput for modern hardware platforms in a restricted space. Such integrated architectures require confidential communication between multiple chips as a key factor for high-performance infrastructures in the 5G era and beyond. Physical layer security is an approach providing information theoretic security among network participants, exploiting the uniqueness of the data channel. We experimentally project orthogonal and non-orthogonal symbols through 380 μm long multimode on-chip interconnects by wavefront shaping. These interconnects are investigated for their uniqueness by repeating these experiments across multiple channels and samples. We show that the detected speckle patterns resulting from modal crosstalk can be recognized by training a deep neural network, which is used to transform these patterns into a corresponding readable output. The results showcase the feasibility of applying physical layer security to multimode interconnects on silicon interposers for confidential optical 3D chip networks.

Filling and reliability of through-silicon via (TSV) are critical issues in the industrialization of TSV. In this study, Sn3.0Ag0.5Cu (SAC305) solder was used to fill TSV instead of the traditional Cu. The purpose of this study was to improve the existing molten metal infiltration method technology which is expected to result in better quality of TSV using solders. A platform for filling quality with SAC305 was designed and constructed. The effect of filling TSV with SAC305 was evaluated using scanning electron microscopy and x-ray. The filling rate and reliability of TSV were significantly improved when the air extraction step was employed before pressure. The productivity of SAC305-TSV increased to 93%. The optimum technological parameters for filling TSV with SAC305 were suggested, and the thermal reliability of SAC305-TSV was analyzed by nano-indentation technology, thermal shock test and aging test. The results showed that delamination and cracking occurred after thermal shock and aging tests, but the problem of protrusion might be improved compared with Cu-TSV. [ABSTRACT FROM AUTHOR]

This brief proposes a wideband interdigital bandpass filter (IBPF), exploiting the through-silicon via (TSV)-based 3-D integrated circuit (3-D IC) technology. IBPF is a structure composed of multiple groups of parallel-coupled line resonators, which can increase the bandwidth and out-band suppression (OBS) characteristics of a bandpass filter. Through the transformation of the Chebyshev low-pass circuit model, a seventh-order IBPF centered at 85 GHz is obtained. By combining TSV technology with the coupling coefficient method, the design process from the Chebyshev low-pass circuit model to the final optimization of IBPF is given. The fractional bandwidth (FBW) of IBPF based on TSV is 63%, the out-of-band suppression is greater than 80 dB, the insertion loss is 1.3 dB, the return loss is 20 dB, and the size of the compact IBPF is only $0.50\times0.34$ mm2 ($0.48\times 0.33\,\,\lambda \text{g}^{2}$). [ABSTRACT FROM AUTHOR]

Chiplet-based packaging technology integrates multiple heterogeneous dies with different functions and materials into a single system as a LEGO-based approach using advanced packaging technology. However, it also brings new challenges in the thermal design aspect and thermal crosstalk between chiplets. In this article, the thermal modeling of a chiplet-based packaging with a 2.5-D interposer was carried out. Two chiplets were mounted on the interposer side-by-side. A Cu lid was attached to the top surfaces of the chiplets and periphery of the interposer through the thermal interface material1 (TIM1) and adhesive, respectively. To further dissipate the heat from the top side, a heat sink was attached to the top surface of the lid through a layer of TIM2. The effects of the TIM type, bonding approach between chiplets and interposer, heat sink structure, thermal crosstalk, convective heat transfer coefficient above the lid, and thermal design power (TDP) were analyzed. The study results show that the bumpless interconnect is beneficial for the heat dissipation of the chiplet-based packaging. The staggered column fin can exhibit superior cooling performance. The short pitch would bring cooling challenges for fine-pitch multiple chiplets integration. The temperature is decreased rapidly first and then slowed down with the increase of convective heat transfer coefficient above the lid. Under 10 000 W/ $\text{m}^{2}\cdot \text{K}$ , the maximum TDP was about 250 W. [ABSTRACT FROM AUTHOR]

A time-interleaved duobinary encoding scheme for the low-power high-bandwidth memory (HBM) I/O interface is proposed with a 65-nm CMOS process. To reduce power consumption in HBM I/O using multiple through-silicon via (TSV) I/Os, a transmitter (TX) that performs duobinary signaling with a voltage-mode driver is proposed. A small area encoder is implemented to generate duobinary output and an edge-boosted pre-driver is proposed to improve the slew rate and the robustness against the process, voltage, and temperature (PVT) variations of the duobinary voltage-mode driver. To convert the duobinary signal into a non-return-to-zero (NRZ) signal, a one-tap decision feedback equalizer (DFE) is used at the receiver (RX). NRZ signal conversion is proposed using one reference voltage and one PMOS switch to reduce the hardware complexity caused by additional reference voltages. An eight-stacked TSV is emulated in the 65-nm CMOS process, and the emulated capacitance of each stack is 100 fF. The energy efficiency of the proposed transceiver chip is 0.373 pJ/b/pF with a 27 – 1 pseudorandom binary sequence at 5 Gb/s. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) integration is considered an effective approach to extend and expand Moore's Law. Among them, Through-Silicon Via (TSV) technology provides mechanical support, heat conduction, and electrical connections for vertically stacked chips. The multilayer interface structure of TSV and the significant differences in the coefficient of thermal expansion (CTE) between layers can lead to complex thermal stress in TSV structures under heating conditions, which can degrade the performance of Three-Dimensional Integrated Circuits (3D ICs). This article systematically summarizes the current research status of copper pillar extrusion protrusions, Cu/Si interface integrity damage, and carrier mobility changes caused by thermal stress, focusing on the failure mechanisms and models of each aspect, elucidating the influencing factors and potential destructive failures. It then outlines and compares the advantages and disadvantages of micro-Raman spectroscopy, bending beam technology, and synchrotron X-ray microdiffraction technology in characterizing thermal stress in TSV structures. Characterizing thermal stress is beneficial for determining stress distribution and reliability risks of TSV. Finally, based on the analysis of the reliability impacts of the three major aspects mentioned above, measures to reduce the reliability impacts of thermal stress from the perspectives of heat dissipation, structure, materials, and processes in recent years are summarized. This article aims to deepen researchers' understanding of the main failure modes caused by thermal stress on TSV structures and provide theoretical guidance for building stable and reliable TSV structures. [ABSTRACT FROM AUTHOR]

• Defect-free Cu bottom-up filling in TSVs is achieved using CTA+ and Br-. • Negative differential resistance (NDR) behavior is observed with CTA+ and Br-. • The effect of CTA+ and Br- on the passive-active transition is investigated. • CTA+ determines the location in TSVs where the passive-active transition occurs. • Br- enhances the suppression with CTA+, preventing void entrapment inside TSVs. Suppressing additives for Cu electrodeposition play a critical role in inducing bottom-up filling in micrometer-scale features such as through-silicon vias (TSVs). This study explores the adsorptive behaviors of cetyltrimethylammonium cation (CTA+) and bromide ion (Br-) and their application to defect-free TSV filling. Electrochemical analyses reveal that both CTA+ and Br- suppress Cu electrodeposition, with only CTA+ exhibiting negative differential resistance (NDR) behavior. The addition of Br- to CTA+ enhances the suppression effect while maintaining the NDR behavior of CTA+. TSV filling experiments demonstrate that the NDR behavior of the CTA+ and Br- combination induces the passive-active transition on the sidewalls of TSVs, which is essential for Cu bottom-up filling. The effects of CTA+ and Br- concentrations on the passive-active transition are also investigated, showing that CTA+ determines the height at which the passive-active transition occurs, while Br- enhances suppression to inhibit Cu growth on the sidewalls in the active region. Based on these behaviors, the optimal CTA+-Br- combination leads to successful bottom-up filling in TSVs. The mechanisms of TSV filling with CTA+ and Br- are suggested based on electrochemical analyses and gap-filling results. The active region at the TSV bottom, formed via selective breakdown of suppressing adsorbates, is filled while effectively inhibiting Cu deposition on the sidewalls, followed by filling the remaining portion of TSVs with vertical Cu growth. [Display omitted] [ABSTRACT FROM AUTHOR]

The performance of three-dimensional integrated circuits is decisively influenced by the thermo-mechanical behavior of through-silicon vias (TSVs), which are subjected to stresses formed during fabrication process as well as cyclic operation as a result of coefficients of thermal expansion (CTEs) mismatch between the silicon substrate, passivation layers, and metallic conduction paths. In this work, we adopted an integrated approach combining micro-Raman, wafer curvature experiments, and finite element (FE) modeling to study the triaxial residual stresses in silicon in the vicinity of W-coated hollow TSVs. A comparison of the experimental and calculated Raman shifts from a TSV cross section allowed a validation of the FE model, which was then extended to a non-sliced TSV. In the next step, the calculated bulk strains were compared with the ones measured using synchrotron X-ray micro-diffraction in order to specifically assess the stress decrease in Si as a function of the distance from the TSV wall within ~25 μm. The experimental verification of the FE model demonstrates the importance of combined experimental-computational approaches to study stresses in micro-scale devices with complex morphology. [ABSTRACT FROM AUTHOR]

Through‑silicon via (TSV) is one of the most important features in 3D integrated circuit (IC) and 2.5D packaging. Both are within the advanced packaging topic for the digital and analog ICs aligned with More than Moore's paradigm. This article revisits the proposal and progress of carbon nanotubes (CNTs) TSV technology that potentially offers an improvement over the conventional Cu TSV. Today, CNTs TSV has never materialized in commercial products of 3D IC and 2.5D packaging. Compilation on notable numerical modeling works and matching them with related issues in fabrication suggest CNTs TSV technology is still in its infant stage. Although the simulation occasionally shows the advantages of CNTs TSV over Cu TSV in both digital and analog circuits, these results are prone to overestimation. One of the culprits is the number of CNT strands in the bundle which at best can be grown in the fab only ∼ 1 % of the theoretically compact bundle used in the RLC and RLGC models. The direction where CNTs TSV is targeting in 3D IC and 2.5D packaging is not clear by several researchers. As the requirements for high-speed digital and high-frequency analog are different, they are important to be sorted out as an essence of this review to project the path of this CNTs TSV technology. • The progress of CNTs in TSV for 3D ICs and 2.5D packaging is reviewed. • RLGC modeling works and issues in fabrication suggest CNTs TSV technology is still in an infant stage. • The high-density CNT forest is only ∼1% of the theoretically compact CNT packing, so the RLGC model is erroneous. • For high-frequency analog, development should focus on Cu-CNTs through glass via (TGV) interposer as 2.5D packaging. • For high-speed digital, CNTs TSVs are not a good replacement for Cu in 3D ICs and interposers of 2.5D packaging. [ABSTRACT FROM AUTHOR]

Remaining Useful Life (RUL) of Lithium-Ion Battery (LiB) While product lifetime can be predicted through reliability tests in most cases, field reliability is likely different. Future Outlook Reliability of products is an implicit expectation from users, but the current quality assurance method is limited to provide sufficient information to assure product reliability. This is a paradigm shift in product reliability assurance, and current reliability evaluation, when performed on the final product, would then act as secondary measurements, confirming the initially predicted reliability [[3]]. Silicon devices are vulnerable to radiation, and to improve the reliability of the radiation system with good electronic control, Gallium Nitride (GaN) devices are suggested. [Extracted from the article]

Through‐silicon via (TSV) technology is a key technology to realize multi‐layer chips and its structure model and transmission characteristics have attracted much attention. With the continuous reduction of chip size, higher requirements are put forward for the model and transmission characteristics of TSV. A novel elliptic cylindrical TSV structure model is proposed. The influence of axial length ratio, height, dielectric layer thickness, and spacing on the transmission characteristics of TSV is further studied by HFSS software. The results show that the transmission of TSV is facilitated by the decrease of axial length ratio, the decrease of height, the increase of dielectric layer thickness, and the increase of TSV spacing. The TSV structural parameter values are optimized by a single variable method. The optimized TSV structure is compared with the original TSV, traditional cylindrical and conical TSV, and coaxial TSV. It is concluded that the elliptic cylindrical TSV structure has better transmission performance. The temperature characteristics of the elliptic cylindrical TSV are simulated. It is indicated that the transmission characteristics of the elliptic cylindrical TSV are poor at low frequency and better at high frequency when the temperature rises. [ABSTRACT FROM AUTHOR]