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Inversion of the yield curve has come to be viewed as a leading recession indicator. Unsurprisingly, some recent instances of inversion have attracted attention from economic commentators and policymakers about possible impending recessions. Using a variety of time series models and recent innovations in econometric method, this paper conducts quasi-real-time forecasting exercises to investigate whether the predictive capability of the yield curve extends to forecasting economic activity in general and whether removing the term premium component from yields affects forecast accuracy. The empirical findings for the US, Australia, and New Zealand show that forecast performance is not improved either by augmenting simplistic models with information from the yield curve or by making such a decomposition of yields. Results from similar research exercises in previous work in the literature are mixed. The results of the present analysis suggest possible explanations that reconcile these conflicting results.

A novel ladder transmission line method (LTLM) that features eliminated parasitic resistance from contact metal and access electrodes, simple fabrication process, and $2\times 10^{-10}\Omega-\text{cm}^{2}$ resolution for highly-accurate extraction of specific contact resistivity $(\rho_{c})$ in the $\sim 10^{-10}$ to 10−9 $\Omega-\text{cm}^{2}$ regime is demonstrated. The current distribution and extraction of $\rho_{c}\text{ln}$ LTLM are verified by TCAD and numerical distributive-resistor-network method, respectively. The extraction error caused by the current spreading and crowding in LTLM are modeled, and design guidelines to achieve 10−10 $\Omega-\text{cm}^{2}$ resolution for $\rho_{c}$ extraction are provided. By applying LTLM to the Ni/p+-Ge 0.95 Sn 0.05 contact, a record-low $\rho_{c}$ down to $4.0\pm 2.0\times 10^{-10}\Omega-\text{cm}^{2}$ was obtained. LTLM is insensitive to variation of metal resistance, unlike the refined TLM (RTLM) which could overestimate $\rho_{c}$ by at least tens of times.

Contact resistance R c in the source/drain (S/D) regions of field-effect transistors (FETs) has increased significantly due to the shrinkage of contact area accompanied with the scaling of device dimensions in the past decades [1] . For the state-of-art transistor technology, the contact area is around 10×10 nm 2 [2] . R c , inversely proportional to the effective contact area, is the main parasitic resistance that limits the on-state current and switching speed of the device in the leading technology. To alleviate the impact of R c , an ultralow specific contact resistivity ρ c of less than 10 −9 Ω-cm 2 is required [3] .

For the first time, Ga ion implantation (Ga I/I) on in-situ Ga-doped Ge (Ge:Ga) and GeSn (GeSn:Ga) films at various temperatures (300 °C, 25 °C, and −100 °C) was investigated. It is found that cryogenic (−100 °C) and room temperature (RT, 25°C) Ga I/I retains strain and the high quality of the GeSn layer after Ga activation while hot Ga I/I (300 °C) degrades the crystalline quality due to the implantation-induced defects. An ultra-low specific contact resistivity $\rho_{c}$ of $8\times 10^{-10}\ \Omega-\text{cm}^{2}$ is achieved for Ti/p+ -GeSn contact by in-situ Ga doping followed by cryogenic or RT Ga I/I while $\rho_{c}$ increases to $2.3\times 10^{-9}\ \Omega-\text{cm}^{2}$ using hot Ga I/I. An ultra-low $\rho_{c}$ of $9\times 10^{-10}\ \Omega-\text{cm}^{2}$ is also demonstrated for in-situ Ga-doped Ge followed by RT Ga I/I. This is the first realization of sub- $10^{-9}\ \Omega-\text{cm}^{2}\ \rho_{c}$ on non-laser-annealed p-type Ge. The sub· $10^{-9}\ \Omega-\text{cm}^{2}\ \rho_{c}$ is thermally stable up to an annealing temperature of 500 °C.

The prevailing of mobile devices continuously drives the demand of advanced System on Chip (SOC) development. To meet the high density, high performance, high reliability, low power and scalability requirements, implant applications have been extensively explored, developed and adopted to bring 10nm device and 7nm FinFET Devices into high volume manufacture. In this talk, the key implant related device challenges for 7nm and beyond will be reviewed. Then, a summary of implant applications which will potentially improve SOC device performance and yield will be presented and proposed. With the novel implant approach, device leakage, reliability, contact resistance, and overall uniformity will be improved.

We report the first demonstration of a nickel silicide (NiSi) contact formation technique using cold silicon (Si) preamorphization implant (PAI) combined with presilicide sulfur (S) implant. The cold Si PAI suppresses the agglomeration of NiSi film at elevated temperatures. Presilicide S implant and its segregation at the interface of NiSi and n-type Si (n-Si) after silicidation significantly lowers the effective Schottky barrier height (Φ n B ) for electrons at the NiSi/n-Si contact. The S atoms in Si could be modeled as donor-like traps near the NiSi/n-Si interface, and a simulation study was performed to explain the reduction of Φ n B caused by S.

The aggressive scaling of semiconductor technologies with each node generates several opportunities for ion implantation solutions to address key scaling challenges (device performance, SCE, leakage, variability, reliability, etc.). Optimization of ion implantation and integration with annealing and other processes is providing pathways for incorporating new materials and device architectures for advanced nodes.

Plasma doping (PLAD), a high-throughput ion implantation technique capable of achieving ultrashallow junctions and conformal doping of 3-D structures such as fin field-effect transistors, is investigated as an alternative to conventional beam-line ion implantation for InGaAs at advanced technology nodes. The PLAD at an elevated substrate temperature (ET-PLAD) is studied and reported for InGaAs for the first time. The ET-PLAD can give lower sheet resistance than room-temperature PLAD due to enhanced dopant incorporation. More crucially, an ET can help to prevent amorphization. After dopant activation anneal, residual corner defects are observed in small fins that are amorphized during plasma ion implantation, whereas fins that remain crystalline during plasma ion implantation are free of corner defects.

Data from the newly-commissioned \textit{Transiting Exoplanet Survey Satellite} (TESS) has revealed a "hot Earth" around LHS 3844, an M dwarf located 15 pc away. The planet has a radius of $1.32\pm 0.02$ $R_\oplus$ and orbits the star every 11 hours. Although the existence of an atmosphere around such a strongly irradiated planet is questionable, the star is bright enough ($I=11.9$, $K=9.1$) for this possibility to be investigated with transit and occultation spectroscopy. The star's brightness and the planet's short period will also facilitate the measurement of the planet's mass through Doppler spectroscopy., 10 pages, 4 figures. Submitted to ApJ Letters. This letter makes use of the TESS Alert data, which is currently in a beta test phase, using data from the pipelines at the TESS Science Office and at the TESS Science Processing Operations Center

In this paper, we first review the trends for advanced CMOS devices in terms of architectures and scalability. The paper highlights the key process challenges for planar MOSFET and FinFET device technologies. We emphasize the need for advanced implant solutions to enable device scaling and performance as well as variability improvement. Especially, we discuss the latest damage engineering solutions as well as materials modification techniques (e.g., contact and strain engineering) to reduce leakage, improve drive current and process margin with reduced variability. Finally, we briefly discuss the implications and new challenges coming from novel channel material devices (e.g., silicon-germanium, germanium, and III–V).

We demonstrate a novel technique to reduce the nickel silicide (NiSi) contact resistance Rcon in strained n-channel MOSFETs (n-FETs) with silicon carbon (Si:C) stressors, where a presilicide aluminum (Al) implant is performed and the Al profile is found to be affected by carbon (C). Al diffusion during silicidation is retarded by the presence of C and a high Al concentration is retained within the NiSi:C film, which is considered to be the main reason for electron barrier height ΦBn reduction in NiSi:C contacts. Ge preamorphization implant prior to Al implant further reduces the ΦBn to 0.44 eV. Integration of this technique in n-FETs with Si:C stressors achieves a 50% reduction in source/drain series resistance and 12% enhancement in saturation drive current. Negligible impact on the device short-channel effects is observed. When Al segregates at the NiSi/Si interface, the hole barrier height ΦBp is lowered, and such an Al profile can be used for the p-FETs. Al profile engineering shows a promise as a single-metal-silicide solution for selective Rcon optimization in CMOS.

The process of modeling pedestrian volume in San Francisco, California, refined the methodology used to develop previous intersection-based models and incorporated variables that were tailored to estimate walking activity in the local urban context. The methodology included two main steps. First, manual and automated pedestrian counts were taken at a sample of 50 study intersections with a variety of characteristics. A series of factor adjustments was applied to produce an estimate of annual pedestrian crossings at each intersection. Second, log-linear regression modeling was used to identify statistically significant relationships between the estimate of annual pedestrian volume and land use, transportation system, local environment, and socioeconomic characteristics near each intersection. Twelve alternative models were considered, and the preferred model had a good overall fit (adjusted R2 = .804). As identified in other communities, pedestrian volumes were positively associated with the number of households and the number of jobs near each intersection. This San Francisco model also found significantly higher pedestrian volumes at intersections (a) in high-activity zones with metered on-street parking, (b) in areas with fewer hills, (c) near university campuses, and (d) under the control of traffic signals. Because the model was based on a relatively small sample of intersections, the number of significant factors was limited to six. Results are being used by public agencies in San Francisco to understand the risks of pedestrian crossings better and to inform citywide pedestrian safety policy and investment.

The 10−7 nm CMOS nodes require that ρc be reduced to < 2E-9 Ω.cm2. Fermi level for most metals is pinned at mid-gap, resulting in a challenge to decrease SBH. There are several implant solutions, such as thermal implants, that can be leveraged to benefit the FinFET doping of SDE, SD and contact module for scaled CMOS.

The purpose of this paper is to present an apphcation of Goal Programming (GP) to the Army Officer Accession Planning problem. The GP model aids the Army’s Officer Personnel Management Directorate ...