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Today, interconnect resistance and reliability are key limiters for the performance of advanced CMOS circuits. As transistor scaling is slowing, interconnect scaling has become the main driver for circuit miniaturization, and interconnect limitations are expected to become even more stringent in future CMOS technology nodes. Current Cu dual-damascene metallization is also becoming increasingly challenging as critical interconnect dimensions approach 10 nm, alternative metallization schemes are researched with increasing intensity for about a decade. The selection of alternative metals is a highly multifaceted task and includes many criteria, covering the resistivity at reduced dimension, reliability and thermal aspects, as well as a sustainability perspective. In this tutorial, we introduce the basic criteria for alternative metal benchmarking and selection, and discuss the current state of the art of the field. The tutorial covers materials close to manufacturing introduction, materials under actual research, as well as future directions for fundamental research. While first alternatives to Cu metallization in commercial CMOS devices have become a reality recently, research for the ultimate interconnect metal is ongoing., Comment: 72 pages, 27 figures

Cu$_x$Al$_{1-x}$ thin films with $0.2 \le x \le 0.7$ have been studied as potential alternatives for the metallization of advanced interconnects. First-principles simulations were used to obtain the Cu$_x$Al$_{1-x}$ electronic structure and cohesive energy to benchmark different intermetallics and their prospects for interconnect metallization. Next, thin Cu$_x$Al$_{1-x}$ films were deposited by PVD with thicknesses in the range between 3 and 28 nm. The lowest resistivities of 9.5 $\mu\Omega$cm were obtained for 28 nm thick stochiometric CuAl and CuAl$_2$ after 400$^\circ$C post-deposition annealing. Based on the experimental results, we discuss the main challenges for the studied aluminides from an interconnect point of view, namely the control of the film stoichiometry, the phase separation observed for off-stoichiometric CuAl and CuAl$_2$, as well as the presence of a nonstoichiometric surface oxide., Comment: 24 pages, 7 figures

Scaling superconducting digital circuits requires fundamental changes in the current material set and fabrication process. The transition to 300 mm wafers and the implementation of advanced lithography are instrumental in facilitating mature CMOS processes, ensuring uniformity, and optimizing the yield. This study explores the properties of NbxTi(1-x)N films fabricated by magnetron DC sputtering on 300 mm Si wafers. As a promising alternative to traditional Nb in device manufacturing, NbxTi(1-x)N offers numerous advantages, including enhanced stability and scalability to smaller dimensions, in both processing and design. As a ternary material, NbxTi(1-x)N allows engineering material parameters by changing deposition conditions. The engineered properties can be used to modulate device parameters through the stack and mitigate failure modes. We report characterization of NbxTi(1-x)N films at less than 2% thickness variability, 2.4% Tc variability and 3% composition variability. The films material properties such as resistivity (140-375 {\Omega}cm) and critical temperature Tc (4.6 K - 14.1 K) are correlated with stoichiometry and morphology of the films. Our results highlight the significant influence of deposition conditions on crystallographic texture along the films and its correlation with Tc., Comment: 8 pages 8 figures

Al$_x$Sc$_{1-x}$ thin films have been studied with compositions around Al$_3$Sc ($x$ = 0.75) for potential interconnect metallization applications. As-deposited 25 nm thick films were x-ray amorphous but crystallized at 190{\deg}C, followed by recrystallization at 440{\deg}C. After annealing at 500{\deg}C, 24 nm thick stoichiometric Al$_3$Sc showed a resistivity of 12.6 $\mu\Omega$cm, limited by a combination of grain boundary and point defect (disorder) scattering. Together with ab initio calculations that found a mean free path of the charge carriers of 7 nm for stoichiometric Al$_3$Sc, these results indicate that Al$_3$Sc bears promise for future interconnect metallization schemes. Challenges remain in minimizing the formation of secondary phases as well as in the control of the non-stoichiometric surface oxidation and interfacial reactions with underlying dielectrics., Comment: 17 pages, 4 figures. Accepted version

The potential of a wide range of layered ternary carbide and nitride MAX phases as conductors in interconnect metal lines in advanced CMOS technology nodes has been evaluated using automated first principles simulations based on density functional theory. The resistivity scaling potential of these compounds, i.e. the sensitivity of their resistivity to reduced line dimensions, has been benchmarked against Cu and Ru by evaluating their transport properties within a semiclassical transport formalism. In addition, their cohesive energy has been assessed as a proxy for the resistance against electromigration and the need for diffusion barriers. The results indicate that numerous MAX phases show promise as conductors in interconnects of advanced CMOS technology nodes., Comment: 26 pages, 4 figures, 4 tables

The temperature coefficients of the resistivity (TCR) of Cu, Ru, Co, Ir, and W thin films have been investigated as a function of film thickness below 10 nm. Ru, Co, and Ir show bulk-like TCR values that are rather independent of the thickness whereas the TCR of Cu increases strongly with decreasing thickness. Thin W films show negative TCR values, which can be linked to high disorder. The results are qualitatively consistent with a temperature-dependent semiclassical thin film resistivity model that takes into account phonon, surface, and grain boundary scattering., Comment: 11 pages, 4 figures

Since the first graphene layer was fabricated in the early 2000's, graphene properties have been studied extensively both experimentally and theoretically. However, when comparing the many resistivity models reported in literature, several discrepancies can be found, as well as a number of inconsistencies between formulas. In this paper, we revise the main scattering mechanisms in graphene, based on theory and goodness of fit to in-house experimental data. In particular, a step-by-step evaluation of the interaction between electrons and optical phonons is carried out, where we demonstrate that the process of optical phonon emission scattering is completely suppressed for all low-field applications and all temperatures in the range of interest, as opposed to what is often reported in literature. Finally, we identify the best scattering models based on the goodness of fit to experimental data., Comment: 7 pages, 5 figures, to be submitted to Journal of Applied Physics

We report on the thin film resistivity of several platinum-group metals (Ru, Pd, Ir, Pt). Platinum-group thin films show comparable or lower resistivities than Cu for film thicknesses below about 5\,nm due to a weaker thickness dependence of the resistivity. Based on experimentally determined mean linear distances between grain boundaries as well as ab initio calculations of the electron mean free path, the data for Ru, Ir, and Cu were modeled within the semiclassical Mayadas--Shatzkes model [Phys. Rev. B 1, 1382 (1970)] to assess the combined contributions of surface and grain boundary scattering to the resistivity. For Ru, the modeling results indicated that surface scattering was strongly dependent on the surrounding material with nearly specular scattering at interfaces with SiO2 or air but with diffuse scattering at interfaces with TaN. The dependence of the thin film resistivity on the mean free path is also discussed within the Mayadas--Shatzkes model in consideration of the experimental findings., Comment: 28 pages, 9 figures

We calculate the resistivity contribution of tilted grain boundaries with varying parameters in sub-10nm diameter metallic nanowires. The results have been obtained with the Boltzmann transport equation and Fermi's golden rule, retrieving correct state-dependent relaxation times. The standard approximation schemes for the relaxation times are shown to fail when grain boundary tilt is considered. Grain boundaries tilted under the same angle or randomly tilted induce a resistivity decrease., Comment: 5 pages, 3 figures in 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

We study the resistivity scaling in nanometer-sized metallic wires due to surface roughness and grain-boundaries, currently the main cause of electron scattering in nanoscaled interconnects. The resistivity has been obtained with the Boltzmann transport equation, adopting the relaxation time approximation (RTA) of the distribution function and the effective mass approximation for the conducting electrons. The relaxation times are calculated exactly, using Fermi's golden rule, resulting in a correct relaxation time for every sub-band state contributing to the transport. In general, the relaxation time strongly depends on the sub-band state, something that remained unclear with the methods of previous work. The resistivity scaling is obtained for different roughness and grain-boundary properties, showing large differences in scaling behavior and relaxation times. Our model clearly indicates that the resistivity is dominated by grain-boundary scattering, easily surpassing the surface roughness contribution by a factor of 10., Comment: 19 pages, 5 figures