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Motivated by the transition to renewable energies in the context of ongoing climate change, offshore wind energy is of rising importance for the energy provision on national and international level. This trend, though, puts pressure on the safety and security community to provide appropriate analyses and solutions in regard to safety and security threats. Based on this motivation, this work investigates the internal disturbances in Offshore Wind Farms (OWF) provoked by cyber-attacks and severe electrical faults that might lead to high impact events. Therefore, the influences of these disturbances are quantified using a simulation model that represents electrical and mechanical aspects as well as the protection and control system. Furthermore, the dependence of the system response on to the disturbance characteristics is determined and the critical values of the disturbance characteristics leading to the OWF service interruption or even physical damage are identified. The results indicate in quantitative manner processes in the electrical and mechanical systems during parameter manipulations due to cyber-attacks and severe electrical faults. This, together with the quantitative signatures of the disturbances, enable future improvements of the security and stability of OWF systems. • Quantitative impact study of manipulations due to cyber-attacks on Offshore Wind Farms (OWFs). • Quantitative impact study of severe electrical faults on service provision of OWFs. • Application of Disturbance Impact Index for vulnerability analysis of OWFs. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we evaluate the full operational cycle of the active-pixel circuit for CMOS image sensors in which four field-effect transistors are suitably combined with an ordinary photodiode; meaning a vertical p–n junction, as opposed to photogates, and with no custom pinned layer. Although this circuit topology itself is not novel, this evaluation intends to shine new light on the use of regular photodiodes. They became largely in disuse in four-transistor image chips under earlier process and design circumstances because the fourth transfer-gate FET did not hold a constant signal long enough and not for a fixed time. Our aim is to investigate the full underlying operational regimen of the transfer gate to propose that a regular photodiode might again be a choice to consider in the four-transistor pixel configuration, not only in conventional imaging but also in dedicated optical applications. The use of an ordinary p–n junction photodiode is advantageous as it offers full compatibility with even elementary mainstream CMOS processes. This investigation resorts to experiments and models both with fabricated integrated pixels and with a macro-pixel circuit implementation. [Copyright &y& Elsevier]

The degradation of SRAM bit-cells designed in a 65 nm bulk CMOS technology in a Sun-Synchronous Low Earth Orbit (LEO) ionizing radiation environment is analyzed. We propose an inflight SEU rate estimation approach based on a modeled heavy ion cross section as opposed to the standard experimental characterization. Effects of irradiation with estimated LET spectrum in SRAM bit cell, i.e. the location of sensitive regions, its tendency to cause upset, magnitude and duration of transient current as well as voltage pulses were determined. It was found with SEU map that 65 nm SRAM bit-cell can flip even if high LET particle strikes in close proximity of bit-cell outside the SRAM bit-cell area. The SEU sensitive parameters required to predict SEU rate of on-board target device, i.e., 65 nm SRAM were calculated with typical aluminum spot shielding using fully physical mechanism simulation. In order to characterize the robustness of scaled CMOS devices, state of the art simulation tools such as Visual TCAD/Genius, GSEAT/Visual Particle, runSEU, were utilized whereas LEO radiation environment assessment, upset rate prediction was accomplished with the help of OMERE-TRAD software. [ABSTRACT FROM AUTHOR]

Space radiation environment at Low Earth Orbits (LEO) with perigee at 300 km, apogee at 600 km altitude having different orbital inclinations was modeled in the form of electrons and protons trapped in Van Allen Earth Radiation Belts (ERBs), heavy ions and protons in Galactic Cosmic Rays (GCRs), and Energetic Solar Particles (ESP) Events during solar maximum period. The co-relation between various shielding thicknesses and particles transport flux was analyzed for this specific orbit. We observed that there is an optimum shield thickness above which the attenuation of the transmitted flux of incident particles is negligible. To estimate the orbit average differential and integral fluxes to be encountered by onboard devices an appropriate radiation environment models were chosen in OMERE-TRAD toolkit and the impact of various shielding thickness for different orbital inclinations on integral Linear-Energy-Transfer (LET) spectra were determined. [ABSTRACT FROM AUTHOR]

Coarse grain reconfigurable architectures (CGRAs) are an emerging hybrid computational architecture that has the parallel customization benefits of low-level logic devices, such as FPGAs and ASICs, while the relative coarseness of these architectures makes CGRAs easier to design for, which is more similar to the traditional processor. In the process of mapping designs to CGRAs, flexible, fast, and adaptive placement and routing (P&R) is fundamental in order to implement efficient run-time reconfigurable frameworks. It is well-known that P&R is an NP-complete problem, and thus, solutions rely on heuristics to achieve quality results with acceptable execution times. CGRA P&R has different constraints compared to traditional VLSI P&R, e.g., path latency balancing and modulo scheduling of loops. In this work, we propose a graph-based P&R approach that uses graph traversals to map designs to CGRAs. Additionally, we parallelize our approach with a graph-based greedy heuristic that executes on a GPU. We compare our proposed P&R approach with the CGRA-ME framework, which implements simulated annealing and integer linear programming placement algorithms. Our results show that this new approach can generate optimal mappings and improve the execution run-time up to several orders of magnitude. Furthermore, considering spatial mapping at the millisecond scale, our GPU approach is one order of magnitude faster compared to the state-of-the-art tool VPR. [ABSTRACT FROM AUTHOR]

This paper presents the Hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology for on-chip communication. Main aspects of this work are the description of the architectural design and the characteristics as well as a comparative analysis against two established indirect topologies namely Butterfly-Fat-Tree (BFT) and Scalable-Minimized-Butterfly-Fat-Tree (SMBFT). Simulation results demonstrate that the proposed topology outperforms its predecessors in terms of performance, area and power dissipation. Specifically, it improves the link interconnectivity between routing levels, such that the number of required links isreduced. This results into reduced router complexity and shortened routing paths between any pair of communicating nodes in the network. Moreover, simulation results under synthetic as well as real-world embedded applications workloads reveal that H-SMBFT can reduce the average latency by up-to35.63% and 17.36% compared to BFT and SMBFT, respectively. In addition, the power dissipation of the network can be reduced by up-to33.82% and 19.45%, while energy consumption can be improved byup-to32.91% and 16.83% compared to BFT and SMBFT, respectively. [ABSTRACT FROM AUTHOR]

Network‐on‐chip (NoC) is a reliable and scalable communication paradigm deemed as an alternative to classic bus systems in modern systems‐on‐chip designs. Consequently, one can observe extensive multidimensional research related to the design and implementation of NoC‐based systems. A basic requirement for most of these activities is the availability of NoC simulators that enable the study and comparison of different technologies. This study targets the analysis of different NoC simulators and highlights its contributions towards NoC research. Various NoC tools such as NoCTweak, Noxim, Nirgam, Nostrum, BookSim, WormSim, NOCMAP and ORION are evaluated and their strengths and weaknesses are highlighted. The comparative analysis includes methods for estimation of latency, throughput and energy consumption. Further, the exemplary real world application, video object plane decoder is mapped on a 2D mesh NoC using different mapping algorithms under NOCMAP and NoCTweak simulators for comparative analysis of the NoC simulators and their embedded mapping algorithms. [ABSTRACT FROM AUTHOR]

A Mesh topology is one of the most promising architecture due to its regular and simple structure for on-chip communication. Performance of mesh topology degraded greatly by increasing the network size due to small bisection width and large network diameter. In order to overcome this limitation, many researchers presented modified Mesh design by adding some extra links to improve its performance in terms of network latency and power consumption. The Cross-By-Pass-Mesh was presented by us as an improved version of Mesh topology by intelligent addition of extra links. This paper presents an efficient topology named Cross-By-Pass-Torus for further increase in the performance of the Cross-By-Pass-Mesh topology. The proposed design merges the best features of the Cross-By-Pass-Mesh and Torus, to reduce the network diameter, minimize the average number of hops between nodes, increase the bisection width and to enhance the overall performance of the network. In this paper, the architectural design of the topology is presented and analyzed against similar kind of 2D topologies in terms of average latency, throughput and power consumption. In order to certify the actual behavior of proposed topology, the synthetic traffic trace and five different real embedded application workloads are applied to the proposed as well as other competitor network topologies. The simulation results indicate that Cross-By-Pass-Torus is an efficient candidate among its predecessor’s and competitor topologies due to its less average latency and increased throughput at a slight cost in network power and energy for on-chip communication. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is an emerging technology, conceived in face of nanoscale limitations of CMOS circuits, with exceptional integration density, impressive switching frequency, and remarkable low-power characteristics. Several of the current challenges toward the progress of QCA technology is related to the automation of the design process and integration into existing design flows. In this regard, this paper proposes the universal, scalable, efficient (USE), and easily manufacturable clocking scheme. It solves one of the most limiting factors of existing clock schemes, the implementation of feedback paths and easy routing of QCA-based circuits. Consequently, USE facilitates considerably the development of standard cell libraries and design tools for this technology, besides avoiding thermodynamics problems. Case studies presented in this paper reveal an area reduction of up to factor 5 and delay decrease by up to factor 3 in comparison with an existing advanced clocking scheme. [ABSTRACT FROM PUBLISHER]