Search

The reliability evaluation of logic circuits is an essential step in the computer-aided design flow of emerging integrated circuits (IC). Due to the increased process variation effects in submicron IC technologies, reliability evaluation should include the transistor-level faults’ modeling and analysis. In this paper, a two-step reliability evaluation method was developed. In the first step, the gate error probability (in a matrix form) was computed based on transistor fault modeling. In the second step, the circuit’s graph was traversed in topological order. Meanwhile, for each gate, the probability of the gate’s output to be in 16 possible states was computed using the gate error probability matrix (calculated in the first step) and the corresponding gate inputs’ probability matrices. The reliability of the circuit’s outputs was extracted from the related 16-state probability matrix. Furthermore, the reconvergent fan-out problem was handled using the concept of correlation coefficients. Various simulations were performed on ISCAS 89 and LGSynth91 benchmark circuits. Compared with MonteCarlo as a reference method, the results indicated a

This study combines extension theory and chaos theory to create a three-level T-type inverter fault diagnosis system that uses single-phase line voltage signals. First, the three-level T-type inverter single-phase line voltage output waveform was measured when faults occurred separately in 12 power transistors. Subsequently, the Lorenz master-slave dynamic error transformation was used to obtain the chaos eye coordinates, which functioned as fault characteristics. Fault diagnosis involved extension theory-based fault categorization. Specifically, fault characteristic values were adopted as the input signal to determine the correlation between chaos eyes coordinates and transistor fault, thereby locating faulty transistors. In summary, this study established a low-cost and fast-operating inverter fault diagnosis system. The system integrates detection results with inverter fault-tolerant control to enable the constant operation of inverters in power generation without derating, thereby greatly enhancing system reliability. Finally, the reliability of the smart fault diagnosis system and fault-tolerant control was verified through measurement results.

Cascaded H-bridge inverter is finding increased attention in the industry and is used in high power multilevel inverter (MLI) based drive system applications. The prospect of faults in MLI increases with an increase in number of power semiconductor devices used for switching. Among the numerous faults in multilevel inverter, the power semiconductor switches are more prone to short-circuit (SC) fault and open-circuit (OC) fault. Owing to the applications of multilevel inverters in high power industrial applications and considering the investment costs and the safety aspects, it’s necessary to develop rapid and accurate fault detection (FD) method. Numerous fault detection methods have been developed for symmetric cascaded H-bridge (CHB) MLI. However, the fault identification strategy is limited to the identification of pair of switches (among which one switch is faulty). OC-FD strategy for symmetric CHB multilevel inverter is presented in this paper. Switches are controlled by Modified Phase Disposition (MPD) Pulse Width Modulation scheme. Here, the output voltage of each H-bridge is used as a diagnostic variable to extract the fault features, which are used for artificial neural network (ANN) training. This fault detection method can efficiently and accurately identify the faulty switch of the symmetric CHB multilevel inverter without any misclassification.

Two-level inverter is extensively used in photovoltaic micro-grid power generation system. The transistor in the two-level inverter works under high stress and is prone to failure. In order to increase the practicability and reliability of photovoltaic micro-grid system inverters, it is necessary to study a fast and accurate fault diagnosis method for inverters. Therefore, this paper proposes a new open-circuit fault diagnosis method for photovoltaic micro-grid inverter. The proposed method has a simple calculation process and only needs to analyze the output current without the use of additional sensors, so the diagnosis cost is low. According to the different changes of output current, the diagnostic variables and adaptive thresholds are calculated for fault diagnosis and location. It can be seen from the simulation report that this method can diagnose the fault of transistor quickly and accurately, and it is robust to load disturbance.

This paper addresses the methods to retain the functionality of the soft-switching current-fed converter in the case of transistor fault. Various primary-side transistor faults and corresponding scenarios to minimize the influence on the converter characteristics are presented. The proposed method allows preserving the power delivery and converter soft-switching operation in the case of fault of one of the primary side transistors. Post-fault operation was experimentally verified using a 500W converter prototype, and resulting implications for converter efficiency were analyzed.

Three phase Voltage Source Inverter (VSI) plays an important role in power electronic applications. Many types of faults occur in it which degrades the performance of the VSI. One possible fault in inverter is open circuit transistor fault. Knowledge of fault mode is extremely important to improve performance of VSI. This paper presents a method of open circuit transistor fault diagnosis which is based on combination of diagnostic variable and Fuzzy Logic. This method can detect single as well as multiple open circuit faults. Diagnostic variables are used to identify faulty phase and an average current is used to identify faulty switches. Fuzzy logic is used to improve performance of system under variable load conditions during faulty conditions.

Renewable energy sources become an increasing alternative power source. Among the available energy sources, Photovoltaic (PV) has a remarkable growth and a significant penetration in many applications. PV-based power supplies are managed by switching power converters and the connected activities will halt when power supply fails. In this paper, we propose an original fault tolerant cascaded step-up step-down converter circuit, under transistor fault. Both open-circuit fault (OCF) and short-circuit fault (SCF) of transistors are considered. The fault tolerant operation of the proposed circuit is based on the following elements: fault tolerant cascaded step-up step-down circuit, transistor fault diagnosis and suitable reconfigurable control. The originality of the proposed fault tolerant circuit lays on implementing a global reconfiguration for the two-cascaded stages, based on a single synchronous redundant transistor. Moreover, the fault detection is based on the waveforms of the inductance currents. An efficient reconfigurable control with fast post-fault management is also proposed. Some selected simulation results are provided to validate the effectiveness of the fault tolerant operation.

This paper proposes novel and simple method of fault-tolerant control of induction motor supplied by a two-level voltage source inverter. The inverter, after the open transistor fault, is reconfigured — the faulted phase is connected to the neutral point of DC link capacitors. The control method is based on sliding mode concept and allows to obtain robust control of motor torque. It does not require space vector modulation, therefore there is no need to make any complex changes after the fault. In this paper, it is proposed to include an additional switching function that ensures balance of the DC link voltages, while the whole control method remains the same. Theoretical study is illustrated using wide simulation tests.

A novel fast open-transistor diagnosis approach for voltage-source inverters (VSI) based on calculated bridge arm pole-to-pole (PTP) voltages is proposed in this paper. The theoretical PTP voltages can be calculated with duty cycle ratio and DC input, and the real PTP voltages can be calculated with output voltages and currents. When no fault occurs, there should be no difference between the theoretical and the real PTP voltages. Once fault happens, great deviations between these two calculated voltages will be incurred and can be utilized to detect and localize the fault. This method is able to achieve fast diagnosing speed, while no extra hardware circuits and complex calculation are needed, thus it can be embedded in the existing control system with little effort. Furthermore, strong robustness against operation variation makes this method feasible in diversified applications. Simulations and experiments have been carried out to validate the correctness and effectiveness of this method.

The increased components requirement to realize multilevel inverters (MLIs) fallout in a higher prospect of fault due to power semiconductor switches. Efficient fault detection and diagnosis (FDD) strategies have to be implemented to guarantee protection as well as the reliable operation of MLIs. This paper presents a novel open-transistor fault detection method in a charge balanced symmetric cascaded H-bridge (CHB) MLI. The method has been formulated based on the simulations and experiments on a charge balanced 5-level CHB-MLI. The proposed method uses the mean value of the bridge voltages as the diagnostic variable. The simulation and experimental results prove that this approach can detect the open-transistor fault and identify the faulty switch pair.

Multilevel inverters (MLIs) consist of increased number of power semiconductor devices for the generation of desired output voltage. As the number of components increases, the probability of fault due to power semiconductors increases drastically. Although the MLI topologies are in a matured state, the research in fault detection and diagnosis (FDD) in MLIs is still in a developing stage. This paper presents the modeling of output voltage under open-transistor fault in cascaded H-bridge (CHB) MLIs. The proposed method can be utilized in the analysis of open-transistor fault in both symmetric and asymmetric configurations of CHB-MLIs. The output voltage modeled using this method for the healthy and open-transistor fault conditions have been verified through simulation and experiments on symmetric and asymmetric CHB-MLIs.

A novel method is presented for the detection and isolation of open-transistor faults in voltage-source inverters feeding AC motors. The method is an extension of the normalized DC-components method. The normalized average currents are combined with additional diagnostic variables which convey information about the percentage of time spent by the phase currents in the near-zero zone. The combined diagnostic signals permit much more robust diagnostics of single-transistor faults and make feasible the diagnostics of multiple-transistor faults. Suggested in this paper is also an alternative solution for the normalization of DC components, which is easier interpreted and simpler to implement.

The number of power semiconductor switches and DC sources will increase with the increase in the number of levels of output voltage of the multilevel inverter. As the number of power semiconductor switches increases, the possibility of its failure and hence the breakdown of the inverter operation also escalate in a nonlinear manner. Hence, the detection of the failure of the power semiconductor switch is of paramount importance, considering the availability and reliability of the system is concerned. The gate unavailability or the transistor open circuit fault detection in asymmetrical multilevel inverter by means of monitoring the mean value of the output voltage is presented in this paper. Simulation of this method is carried out in both binary and trinary combinations of asymmetric multilevel inverter.

To meet increasing demand for higher reliability in power electronics converters applicable in electric vehicles, fault detection (FD) is an important part of the control algorithm. In this study, a model-based open transistor fault diagnsosis method is presented for a voltage-source inverter (VSI) supplying a five-phase permanent magnet motor drive. To realise this goal, a model-based observer is designed to estimate model parameters. After that, the estimated parameters are used to design a sliding mode observer in order to estimate the phase current in an ideal model. Subsequently, the proposed FD technique measures the similarity between the estimated current and real current using cross-correlation factor. This factor is used for the first time in this study to define a FD index in VSI. The presented FD scheme is simple and fast; also, it is able to detect multiple open switch or open phase faults in contrast to conventional methods. On the other side, in order to track reference current of the motor, the estimated parameters are used to design a proportional resonant controller. The FD technique is used to operate a multiphase fault-tolerant brushless direct current (BLDC) motor drive. Experimental results on a five-phase BLDC motor with in-wheel outer rotor applicable in electrical vehicles are conducted to validate the theory.

In this paper a transistor open-circuit fault diagnosis problem in two-level voltage inverter controlled shunt active power filter drives was discussed. Taking into consideration requirements of the contemporary monitoring drive systems original transistor fault diagnostic technique were proposed. Presented results were obtained by designed in PSIM software simulation model.

A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.

A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in CMOS digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck short (short circuit) behavior. In this paper only combinational logic is taken into consideration. The computations are performed at the transistor level directly, i. e., by using the original transistor schematic solely, without any logic conversion. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program.

A new fault model that incorporates both logic and circuit level description is presented. The model, called Logic Transistor Function (LTF), is developed to represent nMOS combinational circuits. The LTF uncovers extensive information about the structure of the circuit, and is utilized to specify the output of the fault-free and faulty circuits with single or multiple transistor stuck faults. The LTF is effective in modelling the sequential behaviour of the faulty combinational nMOS circuit. A procedure that relies on the LTF model is introduced to detect classical and non-classical faults. The circuit is tested by first partitioning the nMOS circuit and then obtaining the primitive D-cubes of the faulty partition. A variant of the D-algorithm may be applied to accomplish detection. The procedure is systematic, thus making it attractive for programming.

To advance the field of electronics prognostics, the study of transistor fault modes and their precursors is essential. This paper reports on a platform for the aging, characterization, and scenario simulation of gate controlled power transistors. The platform supports thermal cycling, dielectric over-voltage, acute/chronic thermal stress, current overstress and application specific scenario simulation. In addition, the platform supports in-situ transistor state monitoring, including measurements of the steady-state voltages and currents, measurements of electrical transient response, measurement of thermal transients, and extrapolated semiconductor impedances, all conducted at varying gate and drain voltage levels. The aging and characterization platform consists of an acquisition and aging hardware system, an agile software architecture for experiment control and a collection of industry developed test equipment.

A novel method is presented for the detection and isolation of open-transistor faults in voltage-source inverters feeding low-power AC motors. The method is based on monitoring two diagnostic signals, one indicating sustained near-zero values of output current and thus permitting fault detection, the other permitting the isolation of the particular transistor which went faulty. The latter signal is the ratio of the average phase current and the average magnitude thereof. The method proves to work reliably, enabling detection and isolation of all possible cases of single and multiple faults. It enjoys high immunity to transients and noise and requires no extra hardware on top of that normally used for basic control purposes.

Several realistic transistor fault models were applied to circuit-level simulation models of code checkers in order to investigate the run-time fault testing capability. Various implementations of checkers designed for the detection of stuck-at faults were examined. A coverage varying from 99% to 100% was obtained for transistor terminal short faults and from 40% to 85% for open faults. A minimum set of four fault models for simulation-based evaluation of the self-testing property is proposed.

Variable speed drives have become industrial standard in many applications. Therefore fault diagnosis of voltage source inverters is becoming more and more important. One possible fault within the inverter is an open circuit transistor fault. An overview of the different strategies to detect this fault is given, including the algorithms used to localize the open transistor. Previous work showed significant differences among the available methods to detect such a fault for a mains side active rectifier. This paper extends the performance evaluation for the inverter connected to the machine with variable stator voltage and frequency. Simulation results are presented. They show the influence of the applied standard field oriented control on the currents during a fault. An experimental setup in the laboratory is used to validate simulation results. Typical detection results are presented including time-to-detection measurements. Robust detection of open transistor faults has been found to be possible

Fault diagnosis of electrical drives is becoming more and more important today, since variable speed drives have become industrial standard in many applications. As an integral part of the drive, many faults occur within the inverter. One possible fault within the inverter is an open circuit transistor fault, whose diagnosis is subject of this paper. The practical performances of several open-circuit fault diagnostic methods are tested in simulation and experiment. An overview of the different strategies is given, including the algorithms used to localize the open transistor. Simulation results are presented and show different capabilities of each diagnostic strategy in terms of effectivity and false alarm resistivity for a voltage source inverter used as an active rectifier. The existing methods are further developed and adapted to a closed loop controlled active rectifier. An experimental setup in the laboratory is used to validate simulation results. Typical detection results are presented including time-to-detection measurements.

This paper proposes a self-checking Cell Logic Block (CLB) that can be used as building block for on-line testable FPGAs. The proposed cell consists, basically, of a 4 input Look-Up-Table (LUT) and a D flip-flop. The CLB is designed using pass-transistor-based multiplexers, either to select the output of the 4-input LUT, or to select signals from other CLBs. The proposed CLB architecture is characterized by a simple circuit to detect incorrect logic voltage levels due to stuck-close and stuck-open faults and by a sensor to test anomalous dissipated currents. In this way, the proposed CLB allows on-line detection of any single transistor fault.

A fault model in the state transition level of finite state machines is studied. In this model, called a single-state-transition (SST) fault model, a fault causes a state transition to go to a wrong destination state while leaving its input/output label intact. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. It is shown that, for an N-state M-transaction machine, the length of the SST fault test set is upper-bounded by 2*M*N/sup 2/ while the length is exponential in terms of N for a checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multilevel implementation of the machine. >

Recently, we have introduced a comprehensive model for detecting single and multiple faults for MOS combinational circuits based on the logic transistor function concept. In this paper, we extend our previous work to cover MOS combinational circuits that have multiple output lines. A new algorithm is developed which is used to generate test vectors that are capable of detecting single and multiple stuck faults in multiple output MOS combinational circuits. We also introduce a new concept where all the transistors in a specific circuit are realized into a number of transistor sets which alleviates the analysis and planning of a test strategy that accommodates a particular test requirement, i.e. detecting a certain transistor fault occurrence, or fits particular test restrictions, i.e. output line limitation. The advantages of this concept in design for testability is outlined. The relationship of fault coverage and output lines is also introduced and analysed.

An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

Even though technological developments in the area of control of voltage source inverter (VSI) have reached a relatively matured state, advances in improving the reliability of VSI is still a developing area. In order to improve safety as well as reliable operation, an effective fault detection and diagnosis method has to be integrated along with the control of inverter-fed systems. In this paper, implementation of open-transistor fault detection and diagnosis in VSI is presented. The current trajectory of phase currents is employed to detect the fault condition and identify the faulty switch. Implementation of this method in a three-phase two-level VSI with the aid of data acquisition card and LabVIEW software is presented with the experimental result.

The problem of testing differential cascode voltage switch (DCVS) circuits is analyzed. These circuits have several potential applications in fault-tolerant, highly available system design due to their inherent self-checking capability. It is shown how concurrent (online) testing of DCVS circuits, which is very effective under single transistor fault assumptions, can be performed. The impact of multiple faults of DCVS circuits is examined, and analytical results are derived. These results indicate that periodic offline tests on DCVS circuits are necessary in order to achieve high multiple-fault coverage. Single-fault test sets and/or pseudorandom vectors were successfully used in the offline tests to detect many of the multiple faults which reduce the efficiency of online tests. The results show the need for a comprehensive mixed-test strategy combining offline and online tests for DCVS circuits. >

In this paper, characteristics of open transistor faults in cascaded H-bridge five-level three-phase PWM controlled shunt active power filter are determined. Phase currents can’t be trusted as fault indicator since their waveforms are slightly changed in the presence of open transistor fault. The proposed method uses H bridges output voltages to determine the faulty phase, the faulty bridge and more precisely, the open fault transistor.

The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in faulttolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with nonsinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).