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In this work, we design and simulate a high performance electrostatically doped dual buried gates power MOSFET (EDDBGP-MOS) structure. The novelty of the proposed device is three folds. Firstly, the n + source and P + body regions of the device are realized using induced charge plasma by employing metal electrodes on the silicon film. The device thus reduces the risk of random doping fluctuations and the formation of highly abrupt junctions during fabrication. The high temperature processes involved in defining the doped regions are not required, thus providing low thermal budget. Secondly, the Gaussian hole plasma profile in the p body region allows increase in drift doping concentration from 5 × 1015/cm3 to 7 × 1015/cm3 resulting in Ron reduction to almost 24% of its uniformly doped counterpart structure, with only a slight reduction in breakdown voltage of the device. The proposed device thus provides 10% increase in the Baliga's figure of merit (FOM1 = BV2/Rsp). Further, the linearly graded Gaussian profile at the source side reduces the source coupling with gate. The gate charge together with the reduced specific ON resistance value provides as good as 19% reduction in Baliga's high frequency figure of merit FOM2 = Rsp.Qsp). As compared to the conventional trench MOSFET structure, the two buried gates in the proposed structure provides low gate drain coupling along with the suppression in parasitic BJT effect. A two-dimensional simulation study of the proposed EDDBGP-MOS device reveals that it outperforms the conventional trench MOSFET device in terms of the performance parameters of power devices, along with the reduced fabrication complexity. [ABSTRACT FROM AUTHOR]

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In this article, enhancement-mode (E-mode) operation is achieved by employing a trench gate on the $\beta $ -Ga2O3 current aperture vertical MOSFETs via Sentaurus TCAD simulation. The performance of the trench gate $\beta $ -Ga2O3 MOSFETs was investigated with different structure parameters, such as trench gate depth, channel doping concentration, and drift layer doping concentration and thickness. The transistor with a trench gate recess (Gr) of 130 nm obtained a high on/off current ratio of $10^{8}$ , an on-current density of 65 A/cm2, a low specific on-resistance ( $\text{R}_{\mathrm {on,sp}}$ ) of 42.5 $\text{m}\Omega \cdot $ cm2, and a breakdown voltage (BV) of 488 V for an E-mode operation. With the thickness of the drift layer increasing to $9.2 \mu \text{m}$ , BV is improved to 721 V, $\text{R}_{\mathrm {on,sp}}$ keeps a low value of 43.5 $\text{m}\Omega \cdot $ cm2 due to the trench gate structure, and the transfer characteristic maintains the same. The thermal characteristics of the proposed MOSFET were studied and the device stability with high temperature was analyzed. The transistor with Gr = 130 nm can keep working in E-mode operation at T = 500 K. The performance of the transistor exhibits its great potential as a high-voltage switch device for power electronic applications.

In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region with its dimensions optimized to get the best Ron-BV tradeoff. The device exhibits a good scaling property without performance degradation, which our previous structure of dual buried gates power MOSFET lacks because of the coupling effect of the two gates. The performance of the dual gates device depends largely on the length of the gates as well as on the separation between them. A performance degradation is observed while scaling it, in order to reduce its specific ON resistance. The proposed single gate device eliminates the coupling effect of the two gates allowing a better scaling of the device together with decreased process sensitivity. The scaling reduces the active area of the proposed device, resulting in the lowering of its specific ON resistance, without any significant change in its breakdown voltage. The reduced gate coupling also allows a high drift doping which further reduces the on resistance. The simulation results using TCAD device simulator shows that the proposed device possess a specific ON resistance of 25.31mohm.mm2 at a breakdown voltage of 68 V, resulting in a Baliga’s Figure-of-merit (FOM1) of 17.99 MW/cm2, which is highest among the other reported non RESURF devices in the literature. This is achieved in parallel with the reduced gate charge resulting in a good reduction in its other figure of merit, FOM2 (RspxQsp).

In this paper, we propose and analyze a single buried gate power MOSFET structure. The structure uses single gate buried under the source and channel region with its dimensions optimized to get the best Ron-BV tradeoff. The device exhibits a good scaling property without performance degradation, which our previous structure of dual buried gates power MOSFET lacks because of the coupling effect of the two gates. The performance of the dual gates device depends largely on the length of the gates as well as on the separation between them. A performance degradation is observed while scaling it, in order to reduce its specific ON resistance. The proposed single gate device eliminates the coupling effect of the two gates allowing a better scaling of the device together with decreased process sensitivity. The scaling reduces the active area of the proposed device, resulting in the lowering of its specific ON resistance, without any significant change in its breakdown voltage. The reduced gate coupling also allows a high drift doping which further reduces the on resistance. The simulation results using TCAD device simulator shows that the proposed device possess a specific ON resistance of 25.31mohm.mm2 at a breakdown voltage of 68 V, resulting in a Baliga's Figure-of-merit (FOM1) of 17.99 MW/cm2, which is highest among the other reported non RESURF devices in the literature. This is achieved in parallel with the reduced gate charge resulting in a good reduction in its other figure of merit, FOM2 (RspxQsp). [ABSTRACT FROM AUTHOR]

In this paper, a crown-shaped trench gate formed by a sidewall spacer in insulated gate bipolar transistors (IGBT) is proposed to improve breakdown voltage. When a sidewall spacer is added to trench bottom corners, the electric field is distributed to the surface of the sidewall spacer and decreased to 48% peak value of the electric field. Thus, the sidewall spacer IGBT improved to 5% breakdown voltage. Another study proposed an additional oxide layer for trench bottom corners and improved breakdown voltage similar to the proposed IGBT. Previous studies have shown degradation in other electrical characteristics. However, this study shows a sidewall spacer IGBT that increases the current over 3% compared to a conventional trench IGBT when the applied gate voltage is under 4 V. Additionally, the turn-off loss characteristic is similar to conventional trench IGBT. Therefore, the breakdown voltage of the IGBT was improved while maintaining similar electrical properties to existing IGBTs through the crown-shaped gate. [ABSTRACT FROM AUTHOR]

An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications. In the proposed SiC LDMOS device, a double-trench gate is introduced to reduce the channel region resistance. And a p-type variation lateral doping (VLD) region is also employed in the drift region, which not only optimizes the surface electric field and improves the breakdown voltage, but also increases the doping concentration of the N-drift region, resulting in a low drift region resistance. So that, the proposed device achieves an ultra-low specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ). Numerical Simulation results show that the ${R} _{\mathrm{ on,sp}}$ of the proposed SiC LDMOS is 3.5 $\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ with a breakdown voltage of ~1460V, which is reduced by more than 46% compared with the conventional field-plate SiC LDMOS with a ${R} _{\mathrm{ on,sp}}$ of 6.6 $\text{m}\boldsymbol{\Omega }\cdot {\mathrm{ cm}}^{2}$ and a breakdown voltage of ~1210V. The transconductance of the proposed device is improved greatly. And the trade-off relationship between the ${R} _{\mathrm{ on,sp}}$ and the breakdown voltage is also significantly improved compared with those of the conventional device and the previous literature.

The insulated-gate bipolar transistor (IGBT) is characterized by metal-oxide-silicon (MOS)-gating, high current density, and high blocking capabilities. The trench field-stop reverse-conducting IGBT (TFR-IGBT) is distinguished from conventional IGBT (CON-IGBT) by trench MOS gate, field-stop layer, and collector-short structure. As a composite structure made of MOS and bipolar junction transistors (BJTs), TFR-IGBT is susceptible to displacement damage (DD). This work reports the DD effects on TFR-IGBT with the fast neutron fluence up to a fluence of 1013 cm−2. The transfer, forward conductive, and forward blocking characteristics are degraded subsequent to neutron exposures. The suppression of the hump current in the transfer curve is observed by neutron-induced damage. This article proposes, from a device physics perspective, the mechanism behind the characteristics degradation from DD in TFR-IGBT. The dependencies of the key parameters on neutron fluence are analytically modeled. Our models provide a good fit to the experimental data of the IGP20N65H5 TFR-IGBT subjected to fission neutrons. [ABSTRACT FROM AUTHOR]

In this paper, an asymmetric semi-superjunction (SJ) insulated gate bipolar transistor (IGBT) is proposed and investigated. The buffer layer of proposed device is split into two unequal segments with decreasing order of doping in x-direction. One segment is moderately doped, named B N (+) , while other is low doped known as B N (-) . Region B N (-) offers maximum flow of carriers, resulting in increase of collector current density with similar breakdown voltage (BV). In off-state, excess electric field exists due to high voltage. This needs to be restricted which is achieved by B N (+) region. In semi-SJ device drift resistance is reduced which gives a better performance in the off-state, leading to the lower turn-off loss. Outcomes of TCAD simulation result show a 50.6% reduction in on-state resistance without degrading the BV. Furthermore, 48.8% and 20.3% reduction in turn-off loss and forward voltage drop, respectively, are also observed. [ABSTRACT FROM AUTHOR]

In this work, a novel trench-gated CAVET featuring a p-GaN island for breakdown voltage improvement is proposed. The p-GaN island inserted between the two p-GaN current-blocking-layer (CBL) constructs a dual-current-aperture vertical transistor (DCAVET), which enables to engineer the electric-field (E-field) distribution in the buried p–n-junction for voltage sustaining. The device operation mechanism and characteristics were investigated by TCAD simulation. By delicately designing the device structural parameters and optimizing the doping concentration, the premature punchthrough and high ${E}$ -field induced avalanche breakdown were effectively suppressed at even higher reverse blocking voltage. The proposed DCAVET achieves excellent balance between punchthrough and avalanche breakdown, delivering a high breakdown voltage of 1504 V and low ${R}_{\text {on,sp}}$ of 0.77 $\text{m}\Omega \cdot $ cm2. The trench gate DCAVET demonstrates a flexible approach to engineer the ${E}$ -field distribution to achieve kilo-volts GaN power transistors. [ABSTRACT FROM AUTHOR]

In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple‐RESURF) and trenched‐gate to design an n‐type laterally diffused metal‐oxide‐semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple‐RESURF or trenched‐gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front‐end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re‐organizing the process steps, re‐using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on‐state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off‐state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut‐off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers. [ABSTRACT FROM AUTHOR]

In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (RON,sp) of 28.53 mΩ·cm2, which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV2/RON,sp of DG SJ-LDMOS is increased by 85.5 %.

A new device design in trench-gate insulated gate bipolar transistor (IGBT) with dual gate control is proposed for high switching controllability with low loss operation. Injection enhancement effect is effective to obtain low power loss operation of IGBTs. However, excess drift carriers limit turn-off dV/dt, and turn-on dI/dt, and the switching controllability by the external gate resistance is degraded. Surface buffer (SB) IGBT with dual gate control is effective to improve the switching controllability, because the hole current can be modulated effectively by the p-MOS control. TCAD simulation results show the SB-IGBT type-II with dual gate control is the best choice for good turn-off and turn-on switching performances. [ABSTRACT FROM AUTHOR]

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (Cgd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (Eox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the Cgd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (Vth) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations.

A new gate structure in the trench-gate insulated-gate bipolar transistor (IGBT) design is proposed and analyzed for power-loss reduction and the suppression of electromagnetic-interference (EMI) noise. Although the turn-off loss and the ON-state voltage drop Vce(sat) are improved by the injection-enhancement (IE) effect, the IE effect caused dynamic avalanche that limits the turn-off loss reduction. In addition, EMI noise is induced by high dI/dt and large surge current due to the negative gate capacitance. This article shows that the dynamic avalanche and the negative gate capacitance can be suppressed by the management of the electric field concentration and hole current flow around the trench gate by the proposed alternated trench-gate (AT) IGBT structure, and both low power loss and good switching controllability can be obtained. The device simulation results show that the AT-IGBT improves the turn-on surge current Isurge-Vce(sat) tradeoff compared with the conventional IGBTs. [ABSTRACT FROM AUTHOR]

A new structure in trench-gate insulated gate bipolar transistor (IGBT) design is proposed and analyzed not only for power loss reduction but also for long-term stability and suppressing electromagnetic interference (EMI) noise using a device simulation. Although turn-off loss and ON-state voltage drop Vce(sat) are improved by injection enhancement (IE) effect, IE effect causes dynamic avalanche that limits turn-off loss reduction and degrades long-term stability by the charge trap at the trench gate oxide interface. In addition, hole current around the gate induces EMI noise due to the negative gate capacitance. This article shows that the proposed surface buffer (SB) IGBT suppresses dynamic avalanche and negative gate capacitance maintaining low power loss by covering the trench gate bottom and hole evacuation from the pMOS channel. [ABSTRACT FROM AUTHOR]

We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al 2 O 3 dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices. Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage. [ABSTRACT FROM AUTHOR]

We propose a new design for covered source–channel tunnel field-effect transistors (CSC-TFETs) with trench gate structures. The I–V characteristics, on/off current ratio, subthreshold swing, and band-to-band tunneling rate are analyzed using a commercial device simulator. Our proposed CSC-TFETs exhibit an on/off current ratio of approximately 1010, an on-current of approximately 10−5 A/μm at room temperature, and a subthreshold swing of less than 40 mV/decade. In addition, the on-current of the CSC-TFETs is ∼233 times that of conventional TFETs, demonstrating that the switching characteristics are superior to those of other silicon-based TFETs. Moreover, a CSC-TFET inverter is characterized by SPICE calibration and provides a high frequency of approximately 1 GHz at a supply voltage of 1.0 V. [ABSTRACT FROM AUTHOR]

SiC super junction (SJ-) MOSFETs have recently gained attention due to their potentially low on-resistance (R ON). In this paper, we conduct TCAD numerical simulations to study SiC non-SJ-MOSFETs, planar-gate (P-) SJ-MOSFETs, and trench-gate (T-) SJ-MOSFETs with voltage levels ranging from 1.5 kV to 15 kV. We focus on the design considerations for SiC SJ-MOSFETs, including on-resistance, gate structure, and oxide shield. Our results reveal that SiC SJ-MOSFETs are suitable for higher voltage level applications (5.5 kV or beyond), unlike non-SJ-MOSFETs, which exhibit extremely high increasing drift resistance with voltage level. The simulations suggest that the T-SJ-MOSFET achieves lower R ON than the P-SJ-MOSFET, mainly due to the narrower p/n pillar in the trench structure, rather than higher channel density. Additionally, it is necessary to fabricate a p-shield in the T-SJ-MOSFET to reduce the oxide field and increase the switching speed. While the gate structure (planar gate or trench gate) has been a focused research topic for non-SJ-MOSFETs, our study highlights the importance of considering the gate structure for SJ-MOSFET design as well. [ABSTRACT FROM AUTHOR]

A design direction in surface buffer insulated gate bipolar transistor (SB-IGBT) is shown for improvement of turn-on switching characteristics, such as switching controllability, current surge and turn-on loss. At turn-on switching, hole current around the gate degrades the switching controllability and induces EMI noise due to negative gate capacitance. However, SB-IGBT can be designed to suppress the negative gate capacitance by enhancement of hole evacuation through pMOS channel. Although turn-on loss can be decreased by small gate-collector capacitance ${C}_{{gc}}$ , the influence of negative gate capacitance is remarkable. Therefore, TCAD simulation results show that high hole evacuation through pMOS channel and optimum ${C}_{{gc}}$ design are effective to improve turn-on switching characteristics. [ABSTRACT FROM AUTHOR]

Based on the construction of the 8-inch fabrication line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor (DMOS+) insulated-gate bipolar transistor (IGBT) technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.

A 600-V snapback-free fast-switching silicon-on-insulator lateral insulated gate bipolar transistor with an embedded self-biased n-MOS (SBM) is proposed and investigated by simulations. The proposed device features an n-MOS which consists of the N+ anode, p-layer, N-buffer, and the anode trench gate (ATG) embedded between the P+ anode and N+ anode. It is worth noting that the ATG is driven by the anode, without any additional control circuits. At the initial conduction stage, p-layer/N-buffer junction acting as electron barrier contributes to snapback-free with a reduced cell pitch. Simultaneously it provides an extra built-in path to extract electrons at the turn-OFF stage, which hence reduces the turn-OFF energy loss (${E} _{ \mathrm{\scriptscriptstyle OFF}}$) and increases the switching speed. Furthermore, the hole leakage current of the SBM LIGBT in the blocking state is suppressed due to the electron accumulation/inversion formed along the sidewall of the ATG, avoiding triggering the P+NP transistor and thus increases the breakdown voltage by 11% in comparison with that of the conventional LIGBT. Simulation results show that the SBM LIGBT reduces ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ by 31% and 43% compared to the conventional LIGBT with the same on-state voltage drop (${V} _{ \mathrm{\scriptscriptstyle ON}}$), at the load current of 100 and 200 A/cm2, respectively. [ABSTRACT FROM AUTHOR]

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (R on_sp ) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a R on_sp of 3.0 mΩ cm 2 . Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices. [ABSTRACT FROM AUTHOR]

In order to enhance specific on-resistance (R on,sp ), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Šimonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics. In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide. The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics. Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized. [ABSTRACT FROM AUTHOR]

This paper discusses the impact of trench depth (Negative Junction Depth (NJD)) and gate length (L G ) shrinking on analog and linearity performance of Transparent Gate Recessed Channel (TGRC) MOSFET with an aim to achieve a reliable and high performance transistor. It is found that device enhances the I ON by 38% and thereby improves the analog performance in terms of transconductance, device efficiency, output resistance, and gain. Moreover, linearity figure of merits are also enhanced at lower gate bias in TGRC MOSFET in comparison to conventional and Conventional Recessed Channel (CRC) MOSFET due to reduced harmonic distortions (g m3 ). Thus, the improved analog and linearity performance at 5 nm NJD and 20 nm L G of TGRC-MOSFET makes it suitable for low power linear RF amplifiers as a nano-scaled device. Thus, these results would serve as a worthy design tool for low power and high performance CMOS circuits. [ABSTRACT FROM AUTHOR]

Comparison of short-circuit (SC) characteristics of 500 V rated trench gate U-shaped channel (TGU) SOI-LIGBT and planar gate U-shaped channel (PGU) SOI-LIGBT is made for the first time in this paper. The on-state carrier profile of the TGU structure is reshaped by the dual trenches (a gate trench G1 and a hole barrier trench G2), which leads to a different conduction behavior from that of the PGU structure. The TGU structure exhibits a higher latchup immunity but a severer self-heating effect. At current density (J C ) < 640 A/cm 2 , the SC destruction is suspected to be latchup-dependent and short-circuit withstand time (t SC ) of the TGU structure is much longer than that of the PGU structure. Due to the high lattice temperature rise caused by the high current density at the emitter side in the TGU structure, the PGU exhibits a better J C -t SC trade-off at J C > 640 A/cm 2 . Comparison of layouts and fabrication processes are also made between the two types of devices. [ABSTRACT FROM AUTHOR]

The technological development of application specific VDMOS and lateral trench power MOSFETs is described. Unlike general-purpose trench vertical DMOS, application specific trench DMOS comprise devices merged or optimized for a specific function or characteristic. Examples include the bidirectional lithium ion battery disconnect switch, the airbag squib driver with safety redundancy, the antilock breaking systems solenoid driver with repeated avalanche operation, and various forms of synchronous rectifiers (including integrated Schottky and pseudo-Schottky operation). Trench lateral DMOS include all implant quasi-vertical, lateral trench, and lateral trench charge balanced devices. Trench power MOSFET packaging addresses multichip surface mount, DrMOS, low inductance, and clip lead packages. [ABSTRACT FROM AUTHOR]

In this paper, we report structural modifications in the conventional laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor on thin silicon-on-insulator by incorporating trenches into the planar technology. The proposed power LDMOS includes two trenches built in the drift region on both sides of the p-base. The gate electrode is placed vertically in the left-side trench, while the right-side trench is filled with oxide. The proposed trench structure suppresses the electric field in the drift region due to the reduced-surface-field effect and allows increased doping concentration to achieve a better trade-off between breakdown voltage and on-resistance. At breakdown voltage of 103 V, the proposed device provides six times higher Baliga's figure of merit, 38% decrease in gate-drain charge, and 9.5 times improvement in dynamic figure of merit as compared with the conventional LDMOS. Further, the proposed device achieves four times reduction in cell pitch as compared with the conventional structure. [ABSTRACT FROM AUTHOR]