164 results on '"Trevisoli, Renan"'
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2. Evolutionary algorithm for minimizing the temperature influence of low power RF Energy Harvesting circuits
3. Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors
4. Electrical parameters and low-frequency noise of AlGaN/GaN high-electron mobility transistors with different channel orientation
5. Junctionless nanowire transistors effective channel length extraction through capacitance characteristics
6. Cross-coupling effects in common-source current mirrors composed by UTBB transistors
7. Interface traps density extraction through transient measurements in junctionless transistors
8. Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors
9. Thermal cross-coupling effects in side-by-side UTBB-FDSOI transistors
10. Optimizing RF Energy Harvesting Systems for IoT Applications using Reinforcement Learning
11. Moving Beyond VHDL in Introductory Computer Architecture Courses: An Exploration of MyHDL as a Modern Alternative
12. Junctionless nanowire transistors parameters extraction based on drain current measurements
13. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
14. Experimental Analysis of HfO2/X ReRAM devices by the Capacitance Measurements
15. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
16. Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors
17. Influence of Interface Traps Position Along Channel in the Low Frequency Noise of Junctionless Nanowire Transistors
18. On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
19. Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors
20. Standard MOS Diodes Composed by SOI UTBB Transistors
21. Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration
22. Variability Modeling in Triple-Gate Junctionless Nanowire Transistors
23. Ultra-Low-Power Diodes Composed by SOI UTBB Transistors
24. Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
25. A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors
26. Trap density characterization through low-frequency noise in junctionless transistors
27. SOI UTBB Capacitive Cross-Coupling Effects in Ultimate Technological Nodes
28. Direct determination of threshold condition in DG-MOSFETs from the gm/ID curve
29. Junctionless Nanowire Transistors Based Wilson Current Mirror Configuration
30. Junctionless Nanowire Transistors Based Common-Source Current Mirror
31. Modeling Schottky Diode Rectifiers Considering the Reverse Conduction for RF Wireless Power Transfer.
32. Modeling Schottky Diode Rectifiers Considering the Reverse Conduction for RF Wireless Power Transfer
33. On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks
34. Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
35. The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime
36. Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature
37. Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion
38. Thermal Cross-Coupling Effects Analysis in UTBB Transistors
39. Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires
40. Correlation between the NBTI Effect and the Surface Potential and Density of Interface Traps in Junctionless Nanowire Transistors
41. Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors
42. Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors
43. Stress Relaxation Empirical Model for Biaxially Strained Triple-Gate Devices
44. Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors
45. Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs.
46. Analysis of the substrate effect by the capacitive coupling in SOI UTBB Transistors
47. Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model
48. UTBB MOSFETs Thermal Coupling Analysis in Technological Node Level.
49. Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors.
50. Physical Insights on the Dynamic Response of SOI n- and p-Type Junc-tionless Nanowire Transistors
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