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Nano-sized unmanned aerial vehicles (UAVs) have been attracting growing attention from both academia and industry with their compact and versatile nature. With the size of merely several centimeters, they are particularly well-suited for executing targeted missions in confined spaces, such as tracking a single pedestrian indoors. However, due to strict constraints on payload and power consumption, the onboard computing unit of nano-UAV is limited to the microcontroller Unit (MCU), which makes the novel single object tracking algorithms not applicable on nano-UAV platform. In this paper, we present a lightweight single pedestrian tracking algorithm to meet the strict resource constraints of nano-UAV system. The algorithm consists of an object detection frontend and a motion-based tracking backend. Based on our deployment methodology, covering from dataset production, model training to layer fusion and deployment, the proposed algorithm achieves extreme complexity reduction (13 × fewer operations and 106 × less memory), and keeps good tracking performance compared with state-of-the-art (SOTA) research work. The full range of onboard experiments illustrate the efficiency our algorithm for real-time tracking (up to 43 fps). Meanwhile, both high computing efficiency (5.2 MACs/cycle) and energy efficiency (5.3 mJ/frame) are achieved and exceed similar works on nano-UAV. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of the architecture of a fraction phase based frequency calibration unit where the number of delay cells (that sense the fraction phase) have been reduced to zero. As no pre-calibration of the delay values are required, it becomes immune to process-voltage-temperature variation. Simulation results for frequency convergence have been provided for different target frequencies of an LC oscillator and for an accuracy of 400 ppm. The paper next presents the design and analysis of a voltage controlled oscillator in the form of an astable multivibrator that is similar to a single stage ring oscillator. A novel resistive tuning technique that occupies small chip area and provides less process variation and more matching has been proposed. Also, it has been shown that although the oscillator's phase noise is worse than LC oscillator, the frequency convergence probability (when using the frequency calibration unit with 4 delay cells, due to the high jitter values) does not degrade significantly with the same calibration unit specifications. Hence successful integration of the oscillator with the calibration unit is possible with the advantage of having fully on-chip design with lower power consumption than that of LC oscillators. The oscillator and the calibration circuit have been designed in UMC 180 nm technology that together consume a current of 320µA (in simulation) from 1.6 V power supply. The designs have been targeted for implant telemetry in the 402–405 MHz band having the requirement of ultra low power consumption. [ABSTRACT FROM AUTHOR]

This letter presents the first duty-cycled low-noise amplifier (LNA) operating in the V-band (40–75 GHz). The amplifier employs a two-stage cascode topology and focuses on low power consumption and therefore fast settling times. The switching is achieved by using inverters at the common-gate (CG) transistor of the cascode stage. This control technique enables adapting the duty-cycle and, therefore, the data rate depending on the required performance. The LNA can be operated in an oversampling mode fulfilling a wake-up function and consuming only 22 μW for a data rate of 294 kb/s or in continuous mode dissipating 3.6 mW. A settling time of 0.6 ns, a rise time of 19 ps, and a fall time of 27 ps have been experimentally demonstrated on a prototype fabricated in a 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology. The measurement results include a peak gain of 18 dB, a 3-dB bandwidth of 18 GHz, an average noise figure (NF) of 4.9 dB within the 3-dB band, and an input 1 dB compression point (P1dB) at 60 GHz of −21.1 dBm. [ABSTRACT FROM AUTHOR]

High power consumption of Field-Programmable Gate Arrays (FPGAs) makes them a less attractive choice for ultra-low-power applications. Depending on the power source, ultra-low-power systems could either be constrained by power (energy harvesting systems) or by energy (battery-powered systems). In this work, we are evaluating four different FPGA tiles to find the one that is better suited for both power-constrained and energy-constrained systems. Ultra-low-power systems apply voltage downscaling to reduce the power consumption. However, the operational limits of different blocks do not allow conventional FPGA to be operated at very low voltage. Therefore, their logic capacity can only be increased by 2–4 times by applying voltage downscaling. In this work, we identified the blocks in FPGA tiles that are vulnerable at low voltage and replace them with alternate circuits. The results indicate that, by slight modifications in the conventional FPGA tiles, logic capacity can be increased up to 8 times, whereas power-delay-product can be reduced up to 74%. • Identified the most power efficient FPGA tile. • Studied the performance and logic capacity tradeoff in different FPGA tiles. • Identified robust look-up-table designs for operating under limited power budget. • Showed the importance of using level converters in power-constrained FPGAs. [ABSTRACT FROM AUTHOR]

In this paper, a Bulk Driven Gain Boosting (BDGB) technique has been analyzed which is further employed in the design of a novel operational amplifier to enhance the gain and at the same time, a nested compensation technique is also used to improve the bandwidth without consuming extra power. The proposed operational amplifier circuit has been designed in sub threshold region and is biased with very less current at the first stage; an extra biasing circuit with gate to drain connected transistors is also designed to bias the last stage. The proposed configuration achieves open loop gain of 70dB, CMRR of 144dB, PSRR of 70dB and the unity gain bandwidth of 11MHz at 5pF load capacitance. The output swing is more than 650mV at 0.8V supply voltage consuming only 2.5µW static power. The gain/swing performance of the proposed low-voltage OPAMP would be therefore good enough not to require another amplifying stage in many high-speed, high swing and low-power applications. [ABSTRACT FROM AUTHOR]

A dynamic circuit design technique on the basis of true single phase logic is presented in this paper to minimize leakage power consumption. The circuit is comprehensively designed by incorporating a pair of diode transistor and a pair of stacked transistors. Active mode as well as idle mode power consumption and delay is analysed at low and high die temperature. 89–17% saving in power delay product is obtained for the same along with higher unity noise gain and reduced voltage bouncing noise. The analysis of the circuit also includes the investigation of voltage variation effect, process corner analysis and sizing effect analysis. The proposed technique is compared with several previously proposed dynamic circuit design techniques and it is found to have best power delay product. Further, it is implemented on 32 output decoder for enduring the technique. Comprehensive simulation using 90 nm technology in cadence specter, shows that the proposed design vanquish conventional and other previously proposed dynamic circuit design techniques in terms of power, delay, noise and robust against parameter and process corner variations. [ABSTRACT FROM AUTHOR]

Highlights • A refined artificial axon-hillock neuron circuit is proposed. • A down-scaling of supply voltage (200 mV), transistors width (120 nm) and feedback capacitance (5 fF) is applied. • The circuit is realized in industrial TSMC 65 nm technology. • Its standby power consumption (11 pW) and energy efficiency (2 fJ/spike) are state-of-the-art. Abstract Artificial Intelligence (AI) applications are developing at a high rate, facing soon a tremendous energy challenge. In this context, the original Axon-Hillock (AH) Artificial Neuron (AN) has been optimized to achieve ultra-low power (ULP) consumption. The membrane capacitance was taken out, and in order to drastically reduce its power consumption, the (feedback) capacitance is lowered to 5 fF, the transistors gate width is reduced to 120 nm and the supply voltage is decreased to as low as 200 mV. Designed and fabricated using 65 nm CMOS Technology, the refined AH neuron features a standby power of 11 pW, and when excited, a power consumption that does not exceed 30 pW for a firing frequency of 15.6 kHz. Its energy efficiency per spike is lower than 2 fJ/spike when the DC power is included (around 1 fJ/spike excluding the DC power), for an area of 31 µm2. These performance confer to this ULP AH neuron a high potential for future development of highly energy efficient Spiking Neural Networks, required to design future neuroprocessors embedded in various applications (smart visual sensors for autonomous vehicles, robotics). [ABSTRACT FROM AUTHOR]

• 2 Transistor negative capacitance inverter requires less transistor count to exhibit hysteresis. • Hybrid Schmitt trigger configurations suffer from difference in NDR and strengths of n- and p-sub-circuits. • Accurate approach to model hysteresis window and minimum supply voltage has been developed. • MFMIS NCFETs can lower the V dd requirement for sustaining hysteresis in Schmitt trigger. • Negative capacitance FET based Schmitt trigger outperforms other topologies because of enhanced feedback made possible through a higher on-to-off current ratio. Through an analytical framework, the work showcases the potential benefits of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) negative capacitance (NC) transistor (T) to enhance the hysteresis width (Δ V H) and reduce the minimum supply voltage (V dd,min) of ultra low power (ULP) subthreshold Schmitt trigger (ST) at shorter gate lengths. Analyzing different ST configurations i.e. 2T (both NCFET), 4T-hybrid (realized through combination of NCFETs and MOSFETs), and 6T (all NCFETs or MOSFETs), leads to the inferences that (i) an inherent negative differential resistance of NCFET can be utilized for hysteresis in 2T-ST circuit, (ii) 4T-hybrid ST is not beneficial for enhancing Δ V H due to a current mismatch between MOSFET and NCFET, and (iii) an optimized 2T-ST and 6T-ST designed with high-permittivity (κ) sidewall spacer (Si 3 N 4) and ferroelectric layer (6 nm) can function at V dd,min of ∼ 55 mV, and ∼ 39 mV, respectively. Results indicate towards potential benefits of realizing ULP subthreshold ST through MFMIS NCFETs without any circuit overhead. [ABSTRACT FROM AUTHOR]

This work proposes a novel demodulation circuit to address the implementation of Wake-Up Receivers (Wu-Rx) in Wireless Sensor Nodes (WSN). This RF demodulator, namely Modulated Oscillator for envelOpe Detection (MOOD), is compatible with both FSK and OOK/ASK modulation schemes. The system embeds an LC oscillator, an envelope detector and a base-band amplifier. To optimize the trade-off between RF performances and power consumption, the cross-coupled based oscillator is biased in moderate inversion region. The proof of concept is implemented in a 65 nm CMOS technology and is intended for the 2.4 GHz ISM band. With a supply voltage of 0.5 V, the demodulator consumes 120 μW and demonstrates the demodulation of OOK and FSK at a data rate of 500 kbps.

This paper presents an electrocardiogram (ECG) processor on chip for full ECG feature extraction and cardiac autonomic neuropathy (CAN) classification. Full ECG extraction is performed using absolute value curve length transform (A-CLT) for $\text{QRS}_{\text{peak}}$ detection and using low-pass differentiation for other ECG features such as $\text{QRS}_{\text{on}}$ , $\text{QRS}_{\text{off}}$ , Pwave, and Twave. The proposed QRS detector attained a sensitivity of 99.37% and predictivity of 99.38%. The extracted $\text{QRS}_{\text{peak}}$ to $\text{QRS}_{\text{peak}}$ intervals (RR intervals) along with QT intervals enable CAN severity detection, which is a cardiac arrhythmia usually seen in diabetic patients leading to increased risk of sudden cardiac death. This paper presents the first hardware real-time implementation of CAN severity detector that is based on RR variability and QT variability analysis. RR variability metrics are based on mean RR interval and root mean square of standard differences of the RR intervals. The proposed architecture was implemented in 65-nm technology and consumed 75 nW only at 0.6 V, when operating at 250 Hz. Ultralow power dissipation of the system enables it to be integrated into wearable healthcare devices. [ABSTRACT FROM AUTHOR]

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET's steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has 91% smaller energy delay product (EDP) and 84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2V VDD. [ABSTRACT FROM AUTHOR]

For transiently powered systems a reliable power management is essential. Power management methods in software allow for run-time decisions about the utilization of system resources based on energy models, performance counters and sensor readings. However, finding precise energy models for peripheral devices can become a tedious and challenging task, as they are subject to hardware/software interactions and complex hardware behavior, often with unknown energy characteristics. In this paper, we tackle these problems for a broad set of cases by creating an automated measurement loop for deriving precise energy costs of driver function calls and their parameters. This becomes possible by using an automata-based modeling scheme, which can easily be implemented into the system software. [ABSTRACT FROM AUTHOR]

This work presents a current reference circuit fabricated in a standard 0.18 μm CMOS technology. The reference current is obtained by applying thermal compensation voltage in the conventional self-biased or beta multiplier-based current reference circuit. Eight prototypes of the proposed architecture were measured which have resulted into the mean reference current of 26.1 nA with the temperature coefficient of 202.1 ppm/°C. These measurements were performed in the temperature range of − 40 to + 85 °C. The circuit is capable of working over the supply voltage range of 1-2 V with the measured mean line sensitivity of 2.18%/V. The maximum measured power dissipation of the circuit is 104 nW at 2 V. [ABSTRACT FROM AUTHOR]

In this work, an ultra low power all-MOSFET based current reference circuit, developed in 0.18 µm CMOS technology, is presented. The proposed circuit is based on the classical resistor-less beta multiplier circuit with an additional temperature compensation feature. The circuit is capable of providing the reference current in a nanoampere range for the supply voltage ranging from 1 V to 2 V in the industrial temperature range of −40 °C to 85 °C. The measurements were performed on 10 prototypes. The measured mean value of the reference current is 58.7 nA with a mean temperature coefficient value of 30 ppm/°C. In addition, the measured mean line regulation is 3.4%/V in the given supply voltage range. The total current consumption of the circuit is 352 nA and the chip area is 0.036 mm 2 . [ABSTRACT FROM AUTHOR]

The development of ultra-low-power (ULP) electronic devices has opened up opportunities for disruptive systems like the Internet of Things (IoT). The main concern is the security and privacy issues of the huge amount of personal, sensitive, or safety-related data being processed in these systems. Ensuring security in these ULP systems poses additional challenges than in computers, because of power and cost constraints and physical accessibility by attackers. To solve these problems, innovations in both software and hardware are needed. This article presents a survey of state-of-the-art hardware designs optimizing the tradeoffs between security, power, and costs (including design and manufacturing). The authors analyze the connections between hardware specs and system demands to bridge the gap between research conducted in different communities. They also identify open problems in designing future ULP secure hardware. [ABSTRACT FROM AUTHOR]

Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here. [ABSTRACT FROM AUTHOR]

A highly energy efficient capacitor switching technique in a successive approximation register (SAR) analog to digital converter (ADC) for biomedical applications is presented. The proposed scheme based on new switching method, which combine the LSB split capacitive technique and monotonic method can reduce the average switching energy by 99.2% compared to the conventional SAR architecture. Besides reducing energy in each comparison cycle, the suggested method also achieves an 8× reduction in total capacitance used in the digital to analog converter over the conventional one with the same resolution. The proposed ADC can find application in biomedical engineering systems and other fields which low power consumption is needed. [ABSTRACT FROM AUTHOR]