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This investigation examines the physical mechanisms that can increase the variability of both p-n junctions and silicon–germanium heterojunction bipolar transistors (SiGe HBTs) at cryogenic temperatures. The important operative mechanisms responsible for device parameter variability include bandgap narrowing due to heavy doping, mechanical stress, and the Ge profile. The impact of direct tunneling on cryogenic parameter variability in SiGe HBTs is also examined. Measurement results are compared with TCAD simulations to provide additional insights, and possible mitigation methods are discussed.

Process sensitivity and variation, such as layer thicknesses, etch dimensions and doping levels are all process parameters that should be well understood when assessing their impact on end of process wafer quality and device performance. Improvements in uniformity of electrical device performance is often not taken into major consideration until a certain maturity level of a technology is reached. In this work, use of technology computer aided design (TCAD) and process compact models (PCM) developed from neural networks demonstrate their utility in process- parameter variation understanding in earlier stages of technology development. A TCAD simulation was built and calibrated to match key electrical performance metrics of an experimental high performance SiGe HBT in 130nm BiCMOS technology, which was the device of focus in this study. Figure 1 includes a TCAD cross section of the device1. Neural net techniques, a machine-learning methodology, the development and deployment of which has grown significantly over the last three decades, is used to expand the scope of TCAD to process variability2-3.The aforementioned calibrated TCAD deck was used to generate training data for the neural network process compact model in place of hardware data. Key process features, as listed in table 1 were a few of the process conditions that were varied from nominal values to characterize the variation in resulting electrical performance. Figure 2 includes a 1D schematic view of the epitaxial layers of the HBT, highlighting some of the process features varied in simulation. The neural network was trained using a data analysis suite using three hidden layers with 16 neurons each to get a best fit to the training data input and output values. The foundation of this approach was a TCAD simulation calibrated to match performance of the nominal HBT device of focus. Key AC and Gummel performance parameters had good agreement with hardware data as illustrated in Figure 3a and b. Thousands of individual TCAD simulations with combinations of varied process feature values were then executed to generate neural network training data in lieu of hardware data- utilizing reported standard deviations of each process parameter. The trends and sensitivity of this data was then reflected in the process compact model, which would provide results for large-scale calculation and analysis. Beta was the electrical parameter of focus in this study, where its changes in process variation (mean and standard deviation) were predicted by the trained PCM. The agreement with hardware electrical parameter Beta with respect to Boron dose in Figure 4 demonstrates how use of calibrated TCAD as a basis can empower prediction of large-scale hardware results without the extent of hardware expense. Use of this tool can be extended to simulate and analyze larger populations than what would be feasible for hardware (in several thousands) to predict the effect of process input changes on uniformity of electrical parameters. Figure 5 demonstrates how the changes in standard deviation of Beta can be predicted as a function of Boron dose variation-through generation of large simulated populations by the PCM. The resulting work on a state-of-the-art SiGe BiCMOS technology demonstrates how specific simulation tools, like TCAD-trained process compact models can be leveraged for enhanced process understanding and improvement. The data generated from these tools can supplement or replace hardware and corresponding data, saving in development costs and associated hours in manpower. They can also enable earlier and more agile decision-making about key production metrics throughout the technology development process. Calibrated TCAD infrastructure, coupled with neural-net technology have potential to fulfill pivotal roles through the timelines of technology development, rather than just being utilized when a technology is mature. References: J. Pekarik et al., "A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications," 2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Coronado, CA, 2014, pp. 92-95. W. Coit, B.T. Jackson & A.E. Smith, “Static neural network process models: Considerations and case studies,” International Journal of Production Research, 1998, 36:11, pp. 2953-2967. Borges, T. Ma, W. Ng, S. Krishnamurthy and L. Bomholt, "Implementation of TCAD-for-Manufacturing Methodology using Process Compact Models," 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai, 2006, pp. 1853-1856. Figure 1

This paper provides insight into the transport mechanisms of the collector current in SiGe HBTs operating at cryogenic temperatures and compares three technology generations of devices. Based on the experimental data, a method to differentiate direct tunneling from quasi-ballistic transport is proposed. Measurements indicate that direct tunneling becomes more significant at cryogenic temperatures. The effects of technology scaling on the direct tunneling were investigated using TCAD. Direct tunneling was found to be sensitive to the base width and the Ge profile. It is predicted that without an increase in the Ge content, direct tunneling may dominate over quasi-ballistic transport at the limits of technology scaling.

We investigate high current stress mechanisms and demonstrate how Auger hot carriers can damage both oxide interfaces and polysilicon regions of the emitter and base. A new current gain enhancement (CGE) effect is proposed, which involves hot-carrier damage to the polysilicon emitter and extrinsic base leading to the degradation of the associated minority carrier mobilities. We demonstrate the different CGE mechanisms in SiGe HBTs under forward and inverse modes of operation. The hot-carrier damage responsible for CGE at high injection is explored in depth with the help of TCAD simulations. Evidence for this effect has been gathered with good statistical significance from various stress conditions, various technologies, complimentary (NPN + PNP) devices, and from dc and ac measurements. The new polysilicon degradation mechanism proposed in this paper has been generalized and is important for accurately modeling the changes in base resistance and current gain ( $\beta$ ) at high injection, where circuits are typically biased to extract maximum device performance.

The implementation of a “superjunction” collector design in a silicon–germanium heterojunction bipolar transistor technology is explored for enhancing breakdown performance. The superjunction collector is formed via the placement of a series of alternating the p/xn-doped layers in the collector-base space charge region and is used to reduce avalanche generation leading to breakdown. An overview of the physics underlying superjunction collector operation is presented, together with TCAD simulations, and a parameterization methodology is developed to explore the limits of the superjunction collector performance. Measured data demonstrate the limitations explored in simulation.

The doping profile of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) is modified to enhance inverse-mode (IM) device operation. Device improvements are presented in this paper, along with the impact the alterations have on the radiation effects response. This investigation represents the first published occurrence of a radiation-hardening-by-process approach in a SiGe HBT technology. Results show that improving IM performance can degrade the radiation tolerance of the structure. Total ionizing dose and single-event transient (SET) results are provided along with an analysis that utilizes TCAD simulation. An additional profile modification using an implanted vertical superjunction is included in this paper to expand upon how nonradiation specific device modifications can impact SETs.

Safe-operating-area (SOA) in a high-voltage complementary silicon–germanium (SiGe) (= n-p-n + p-n-p) on silicon-on-insulator (SOI) technology is investigated from 24 °C to 300 °C. Three key reliability degradation regions are identified, including: 1) high-current; 2) mixed-mode; and 3) high-power. The degradation mechanisms, which are operative, including Auger damage, mixed-mode damage, and electrothermal runaway as well as their temperature dependences are identified. Mixed-mode damage exhibits a strong negative temperature coefficient for both n-p-n and p-n-p SiGe heterojunction bipolar transistors (HBTs) up to 300 °C, which leads to an increase in the SOA from a high-voltage perspective. Electrothermal boundaries are also explored by finding ${J}_{C,{\textsf {crit}}}$ and ${V}_{{\textsf {CB}},{\textsf {crit}}}$ across the ${J}_{C}$ – ${V}_{\textsf {CB}}$ plane up to 300 °C. Both n-p-n and p-n-p SiGe HBTs show an increase in the SOA for the electrothermal boundary as temperature increases. High-current-induced damage, on the other hand, exhibits a positive temperature coefficient, which implies that high current drive should carefully be considered when using SiGe HBT circuits operated in a high-temperature environment. However, at very high temperatures (>200°C), the high current damage processes show annealing properties, which implies that at sufficiently high temperatures, annealing can dominate over Auger damage and potentially extend the SOA of the technology.

Total ionizing dose (TID) effects are evaluated for a high-voltage (>30 V) complementary SiGe on SOI technology. Devices are irradiated with 10-keV X-rays at doses up to 5 Mrad(SiO2). The results depend strongly on collector-to-emitter bias, in both forward- and inverse-mode. An anomalous reduction in current gain at high injection in forward-mode operation is observed at doses >500 krad(SiO2). Calibrated 2-D TCAD simulations suggest that this high injection phenomenon is primarily due to interface traps near the STI/Si interface, which is exhibited as a collector resistance increase in the forward Gummel characteristics. Additionally, a strong collector doping dependence is observed, which indicates that this is primarily driven by the thick and lightly doped collector used in this technology. These results illustrate, that high concentrations of interface traps at the STI can have a strong impact on the forward-mode TID response of SiGe HBTs.

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability.

We present measurement results of commercially-available 90-nm SiGe HBTs at 300 K, 78 K, and 7 K. The data reveal increased variability of SiGe HBTs at 78 K and 7 K compared to that at 300 K. The variation of collector current, base current, and DC current gain (β) increase from 5% at 300 K to 50% at 7 K around the average measured values. Transconductance (g m ) variation increases from 0.6% at 300 K to 5% at 7 K. Peak f T variation increases from 2.6% to 7.1%, while the f T at low injection increases from 1.8% at 300 K to 24.9% at 7 K. Increased variability is observed at lower injection levels at 78 K and 7 K and DC parameters tend to have more variation than RF parameters. The implications of increased variability for circuit designs supporting emerging cryogenic applications such as quantum computing are discussed.

This paper presents an overview of the reliability differences of devices optimized for high-performance (HP) and medium-breakdown (MB) in SiGe HBT technologies. To explore the physics of failure, a MB variant in a fourth-generation SiGe HBT technology is described from a processing standpoint to understand any subtle distinctions between its HP counterpart. Reliability stress measurement data is shown to provide insight into the differences between HP and MB SiGe HBTs when biased under high-current and mixed-mode stress conditions. TCAD simulations are presented to aid in the physical understanding of Auger generation/recombination rates, impact ionization rates, and power density across a wide range of conditions where these devices are typically biased and used.

The capability of inverse-mode (IM) silicon- germanium (SiGe) heterojunction bipolar transistors (HBTs) for the mitigation of single-event transients (SETs) under large-signal operation was investigated in an RF down-conversion single- balanced mixer using a through-wafer, two-photon absorption pulsed-laser beam experiment and TCAD heavy-ion simulations. The IM SiGe HBTs replace conventional forward-mode (FM) SiGe HBTs in the differential pair, which provides full current steering for frequency mixing operation. Under steady-state conditions, the IM SiGe HBT differential pair exhibits smaller transient peaks with shorter durations compared to the FM SiGe HBTs. In addition, under the injection of a local oscillator (LO) signal with large swing, the IM SiGe HBTs show faster recovery (50% reduction in the best case) from the impact of SETs. In the frequency domain, it is observed that IM SiGe HBTs produce less distortion at the output for an intermediate frequency below 1 GHz. Based on the performance comparison between FM and IM SiGe HBT down-conversion mixers, system design guidelines to compensate the noise figure degradation associated with using IM SiGe HBTs are discussed.

This paper investigates single-event effects in a W-Band (75-110 GHz) SiGe HBT down-conversion mixer intended for use in a space-based remote sensing radar system. Transient pulse propagation to the output of the mixer as a linear time variant system is analyzed theoretically. This study facilitates the understanding of transient propagation in RF receivers. Device- and circuit-level simulations were conducted to verify the results of the proposed theory. A two photon absorption laser was used to induce transients on different SiGe HBTs within the circuit to assess the impact of SETs on performance. This study shows that significant transients can be produced at the output of the mixer, which can potentially corrupt the received data or received pulse of the radar. It is shown that a differential double-balanced structure can effectively eliminate some of the transients at the output of the mixer. To the authors' best knowledge this is the first study of single event transients conducted on a millimeter-wave SiGe circuit.

The effects of negative feedback, both external and internal, on single event transients (SETs) in SiGe HBT analog circuits are investigated. In order to examine internal negative feedback effects, basic common-emitter NPN current mirrors, with and without emitter degeneration resistors, are utilized. A Wilson current mirror and a Wilson mirror with its intrinsic external feedback removed are used to study external negative feedback effects under the influence of laser-induced single events. The measurement data clearly show notable improvements in SET response that can be made by employing both internal and external negative feedback. The peak transient in the output current is reduced, and the settling time upon a laser strike is shortened significantly by negative feedback. All four investigated current mirrors were fabricated with IBM 8HP 130 nm SiGe BiCMOS technology.

This paper uses a physics-based TCAD degradation model to examine the accumulated stress damage of SiGe HBTs under pseudodynamic mixed-mode stress as a function of both electrical stress bias and temperature. The temperature dependence of mixed-mode stress damage is fully explored, beginning with impact-ionization calibration, and then by identifying and calibrating the dependence of scattering length and hydrogen diffusion parameters of the degradation model. After calibrating the model across electrical bias and temperature, the effectiveness and limitations of accumulated stress damage while varying electrical bias and while varying temperature are identified, and the implications of this aging model for circuit designers are discussed.

We investigate and compare the hot-carrier degradation of SiGe HBTs under both traditional mixed-mode electrical stress conditions and high-current electrical stress conditions using measured stress data and an in-depth analysis of the underlying degradation mechanisms. While large electric fields are the driving force in mixed-mode hot-carrier degradation, the Auger recombination process is shown to be the hot-carrier source under high-current stress conditions. Auger hot-carrier degradation shows a positive temperature dependence, unlike mixed-mode degradation, due to the temperature dependence of Auger recombination and its energy distribution function. We also use calibrated TCAD simulations to explain an unexpected stress threshold behavior that occurs due to the formation of a potential well in the neutral base region, and to explore a field-compression effect at the collector/subcollector junction that contributes to trap formation at the shallow trench isolation oxide interface.

This paper presents the results of an investigation of the steady-state safe operating conditions for large-signal silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) circuits. By calculating capacitive currents within the intrinsic transistor, avalanche inducing currents through the transistor junctions are isolated and then compared with dc instability points established through simulation and measurement. In addition, calibrated technology computer-aided design simulations are used to provide further insight into the differences between RF and dc operation and stress conditions. The ability to swing the terminals of a SiGe HBT beyond the static $I$ – $V$ conditions coincident with catastrophic breakdown is explained. Furthermore, hot-carrier effects are also compared from multiple perspectives, with supporting data taken from fully realized $X$ -band and $C$ -band cascode driver amplifiers. This analysis provides microwave circuit designers with the framework necessary to better understand the full-voltage-swing potential of a given SiGe HBT technology and the resultant hot carrier damage under RF operation.

A SiGe RF low-noise amplifier (LNA) with built-in tolerance to single-event transients is proposed. The LNA utilizes an inverse-mode SiGe HBT for the common-base transistor in a cascode core. This new cascode configuration exhibits reduced transient peaks and shorter transient durations compared to the conventional cascode one. The improved SET response was verified with through-wafer two-photon absorption pulsed-laser experiments and supported via mixed-mode TCAD simulations. In addition, analysis of the RF performance and the reliability issues associated with the inverse-mode operation further suggests this new cascode structure can be a strong contender for space-based applications. The LNA with the inverse-mode-based cascode core was fabricated in a 130 nm SiGe BiCMOS platform and has similar RF performance to the conventional schematic-based LNA, further validating the proposed approach.

This paper presents an overview of the various failure mechanisms observed when a SiGe HBT is operated outside of traditionally-defined electrothermal safe operating areas (SOAs). The concepts of hard and soft safe operating area (SOA) boundaries are defined in this work. This provides two different viewpoints which determine the degradation and failure of a SiGe HBT as a function of bias conditions. Measurements were performed on state-of-the-art SiGe HBTs to measure the hard SOA boundaries in terms of physical parameters such as geometry, layout configuration, and temperature. The outcomes of this work can serve as the stepping-stone to a “red flag” warning mechanism for the detection of hard SOA boundaries within a circuit design environment.

The implementation of a “superjunction” collector design in a silicon-germanium heterojunction bipolar transistor is explored for enhancing breakdown performance. The superjunction collector is formed through the placement of a series of alternating pn-junction layers in the collector-base space charge region to modify the carrier energy profile and reduce avalanche generation. An overview of the physics underlying superjunction collector operation is presented with TCAD simulations, and practical superjunction design techniques are discussed. The first measured data on a superjunction collector is also presented and shows a 57% improvement in breakdown performance.

High-current pulsed stress measurements are performed on SiGe HBTs to characterize the damage behavior and create a comprehensive physics-based TCAD damage model for Auger-induced hot-carrier damage. The Auger hot-carrier generation is decoupled from classical mixed-mode damage and annealing on the output plane by using pulsed stress conditions to modulate the self-heating within the device under stress. The physics of high-current degradation is analyzed, and a temperature dependent degradation model is presented. This model is the first of its kind in both the CMOS and bipolar communities and solves a significant portion of the puzzle for predictive modeling of SiGe HBT safe-operating-area (SOA) and reliability.

We study mixed-mode stress degradation in SiGe HBTs using a novel physical TCAD model in which the processes of hot carrier generation within the semiconductor, carrier propagation to the oxide interface, and formation of interface traps are directly modeled. Transient degradation simulations using a calibrated 2-D SiGe HBT model correlate well with measured data. With this novel simulation tool, we investigate the bias dependence and location of interface traps and show that secondary holes produced by impact ionization are the dominant carrier to damage the emitter-base (EB) spacer oxide interface, confirming previously reported results. We also compare in detail trap formation at the EB spacer and shallow-trench-isolation (STI) oxide interfaces as a function of time and stress condition. At the STI oxide interfaces, we find that hot electrons and holes each dominate trap formation in different regions, and the hot carriers that reach the STI predominately originate outside of the selectively implanted collector, revealing the important role played by dopant diffusion from the extrinsic base of quasi-self-aligned SiGe HBTs.

Profile optimization techniques are investigated for silicon-germanium heterojunction bipolar transistors (SiGe HBTs) intended for inverse-mode (IM) operation. IM device operation, also known as inverse active, involves electrically swapping the emitter and collector terminals and has been shown to improve the radiation tolerance of SiGe HBTs to single event transients (SETs). Multiple profile design variations are explored and trade-offs are analyzed with support of TCAD simulation. Modest design variations show marked improvement on IM performance while having minor impact on forward-mode (normal active) operation.

This paper investigates the RF reliability of SiGe HBT cascode driver amplifiers. By subtracting capacitive currents internal to the common-base device from its collector waveform, a more accurate depiction of electrical stress in the I-V plane is achieved, and from this revised load line, RF stress data is better correlated to DC stress data. This novel analysis technique provides a framework for designers to simulate the effects of RF stress using DC data from both TCAD models and measurements, allowing for optimized performance in high power and high frequency applications where reliability concerns often lead to under-utilization of the transistor's capabilities.

We study the accumulated degradation of SiGe HBTs under time-dependent mixed-mode stress using a new physics-based TCAD degradation model that simulates hot carrier generation and propagation to oxide interfaces, resulting in trap formation. We calibrate the avalanche generation and also do a multipoint calibration of damage on the I-V output plane to accurately predict the accumulated stress damage for a single device over multiple bias points. Looking at the region of the output plane dominated by trap formation, we show that accumulation of traps can be path-independent as long as trap availability is not limiting. We demonstrate this with good correlation between simulation and measurement.