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Finite element modelling is a modern and efficient way to perform stress-strain analyses on both simple components and complex structures. If the material properties are properly set, the software can also model the deformation of parts. A very important criterion of accurate finite element calculations is an appropriate material model. The stress–strain function recorded during the tensile testing of standard specimens shows that stress is not constant during deformation and so it can be specified with a function in finite element software. Often, in finite element modelling, a bilinear model is used to simplify this function. The aim of this paper is to show the difference between the bilinear model, the multilinear model (the model split into several sections the stress-strain curve) and the real function in the analysis of deformation in hardness testing. We also analyse the minimum density of meshing which still provides acceptable accuracy in hardness testing calculations.

In this study, the effect of the magnitude of inherent strain is examined for the simulated deformations of printed specimens, where the material grade is either of MS1 or 316L steel powders. While both material qualities are steel grades, and the same sets of inherent strain values with different magnitude and directional variations are defined in the simulations, allowing isotropic and orthotropic behaviour too, the resulting deformation in the printed part may also be strongly influenced by the mechanical properties of the different steel grades.

In our study, the base material was the aluminium alloy of Al8006. Its application area covers amongst others the material for multilayer tubes. This alloy has been subjected to different technological paths consisting heat treatments (homogenization) and mechanical strengthening technologies: multiple forging, equal channel angular pressing. The aim of the technological paths was to refine the primary phase structure, and to look for the technology sequence that assures the highest strength and the highest toughness at the same time. To determine this, a complex performance index has been created that integrates these property characteristics.

Good-quality ultrashallow n + p junctions are formed using 5-keV amorphizing As+ implantations followed by a single-shot excimer laser anneal for dopant activation. By using an implant that is self-aligned to the contact windows etched in an oxide isolation layer, straightforward processing of the diodes is achieved with postimplantation processing temperatures kept below 400°C. A possible source of junction leakage at the perimeter caused by dip-etch enlargement of the contact window, also confirmed by transmission electron microscopy (TEM) analysis, is identified, and diode performance is improved by increasing the junction/contact window overlap. The optimum performance in terms of low leakage, shallow junctions, and low resistivity is achieved for 30° tilted implants and by applying a thin laser-reflective aluminum layer. This work isolates the minimum requirements for achieving low-leakage diode characteristics.

In the past it has been shown that ultrashallow junctions with minimum lateral dimensions can be made by implanting self-aligned to the contact window and using one-shot excimer laser annealing (ELA) to activate the dopants. Besides the recrystallization of the implanted Si, the final structuring at the contact window perimeter is very important for the ideality of the diode. In this paper this process is has been investigated for 5 keV As+ implanted in windows etched in a thermal/LPCVD oxide layer stack. The window perimeter processing is very critical but tilted implants can be used to increase the junction overlap with the window and good diode characteristics are obtained. The junction depths have been analyzed by secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM). A junction of only 15 nm deep with a sheet resistance of 311 Ω/square was obtained for an implantation tilt angle of 45o and laser energy density of 1000 mJ/cm2, whereas the junction depth of 20 nm and sheet resistance of 220 Ω/square was obtained for the tilt of 7o.

This paper reviews special RF/microwave silicon device implementations in a process that allows two-sided contacting of the devices: the back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the improved device performance that can be achieved. In particular, high-quality SOG varactors have been developed and an overview is given of a number of innovative highly-linear circuit configurations that have successfully made use of the special device properties. A high flexibility in device design is achieved by two-sided contacting because it eliminates the need for buried layers. This aspect has enabled the implementation of varactors with special Ndx -2 doping profiles and a straightforward integration of complementary bipolar devices. For the latter, the integration of AlN heatspreaders has been essential for achieving effective circuit cooling. Moreover, the use of Schottky collector contacts is highlighted also with respect to the potential benefits for the speed of SiGe heterojunction bipolar transistors (HBTs).

Advanced micro-mechanical characterization methods provide material properties of thin films for modeling thermo-mechanical behavior of thin films for micro-electronic applications. Here, we focus on the local measurement method of nanoindentation for finding visco-elastic properties, and a global method of substrate curvature testing that provides linear elastic properties. Our specimen SiLK, Dow chemicals, is a low-k dielectric thin polymer film with a thickness of 400 nm, 6 and 8 μm, deposited on Si substrate. Our results show temperature dependent linear elastic and linear visco-elastic material properties for thin film materials.

The thermo-mechanical integration of polymer films requires a precise knowledge of material properties. Nanoindentation is a widely used testing method for the determination of material properties of thin films such as Young’s modulus and the hardness. An important assumption in the analysis of the indentation is that the indented medium is a semi-infinite plane or half space, i.e., it has an “infinite thickness.” In nanoindentation the analyzed material is often a thin film that is deposited on a substrate. If the modulus ratio is small, (soft film on hard substrate) and the penetration depth is small too, then the Hertzian assumption does not hold. We investigate this situation with spherical and conical indentation. Measurement results are shown using spherical indentation on a visco-elastic thin polymer film and a full visco-elastic characterization is presented.

In microelectronic industry, thin polymer layers are one of the more commonly used product constituents. Examples are glue layers, coatings, and dielectric layers. The thicknesses of these films vary from a few tens of nanometers to over a hundred micrometers. Since at film thicknesses below 100nm the thermal and mechanical properties start to deviate from those in the bulk, adequate characterization techniques are required. In the present paper we will report the results of an extensive literature search on the state-of-the-art of thermo-mechanical thin film characterization methods, such as the substrate curvature test, nanoindentation technique, bulge test, and impulsive stimulated thermal scattering.

More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase the importance of thermomechanical reliability, as confirmed by the ITRS (International technology roadmap for semiconductors; [1] ). Since most of the thermomechanical problems initiate in the design phase, failure prevention-designing for reliability, is strongly desired. To support wafer backend process development, it is necessary to develop reliable and efficient methodologies (both testing and modeling) to predict the thermal and mechanical behavior of backend processes. This paper presents our research results covering the backend process reliability modeling considering both thermal and mechanical (CMP) loading. The emphasis is particularly on the effect of using Cu/SiLK low-dielectric-constant (low- k ) structure instead of the traditional Al/SiO 2 . SiLK is a particular polymeric low- k material developed by the Dow Chemical Company [2] [Adv. Mater. 12 (2002) 1767]. Our results shows that Cu/SiLK structures exhibit significantly different reliability characteristics than their aluminum predecessors, and that they are more critical from several design aspects. This not only makes the stress management in the stacks more difficult, but also strongly impacts packaging.

A possible strategy is described for hot rolling process development, initiated by the response to market demands and considering elements of materials science and engineering. Out of the elements, physical and mathematical simulations play a substantial role, and the effectiveness of technical development is determined by the level of application of simulation techniques.

Integration and properties of devices processed by excimer laser annealing are presented. The best results are achieved by shallow implantations into a native-oxide-free silicon surface and laser annealing with the remainder of the device protected by an Al reflective layer. Low- temperature MISFETs are fabricated with a metal- gate high-k gate stack of PECVD SiO2 and ALD Al2O3 with an EOT of 9.2 nm and an Al-gate. The source/drain regions are self-aligned to the metal gate, which also serves as a laser masking reflective layer. Ablation of the masking layer is prevented due to the low thermal resistance of the thin underlying gate dielectric. The measured devices exhibit good current drivability, which improves with higher laser energy. The maximum processing temperature of the presented MISFETs is 400 C and can potentially to be reduced down to 300 C.

This paper reviews special RF/microwave silicon device implementations in the back-wafer contacted Silicon-On-Glass (SOG) Substrate-Transfer Technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the device level aspects of the SOG process. In particular, complementary bipolar device integration and high-quality varactors for high-linearity adaptive circuits are treated in relationship to developments in back-wafer contacting and the integration of AlN heatspreaders.

This paper reviews several novel process modules developed for the processing of the backside of the wafer of our substrate-transfer technology called back-wafer-contacted silicon-on-glass (SOG), which is in use for fabricating RF/microwave devices such as high-quality varactors and bipolar transistors. In this technology the silicon wafer is transferred to glass by gluing. The integrity of the acrylic adhesive limits the subsequent processing temperatures to less than 300°C. Ultra-low-temperature process modules have therefore been developed to nevertheless allow the creation of low-ohmic contacts and high-quality ultrashallow junctions. Moreover, a physical-vapor deposition of AlN provides an effective means of integrating a thin-film dielectric heatspreader.

Reduced pressure CVD of arsenic has been investigated as a source of dopants in combination with excimer laser annealing (LA). Energy densities used for LA are above the Si melt limit and abrupt, highly doped, nearly defect-free, ultrashallow junctions have been formed. The junction depth is determined by the melt depth and is independent of the doping level, which is determined by the As deposition. Multiple LA of the surface deposited As layer was performed to yield improved uniformity while multiple cycles of As deposition plus LA have been performed to yield a higher dose and consequently lower sheet resistance, which in the case of three depositions drops to around 80 Ω/sq for layers of an estimated depth of less than 20 nm. Near-ideal diode characteristics have been measured.

In this work we present a novel self-aligned emitter-base structure featuring an implanted and laser-annealed emitter region. Using electrical measurements on SiGe NPN HBTs, it is shown that such a process completely eliminates the TED-induced out-diffusion of the boron in the base region while also achieving an ultra-shallow abrupt emitter-base junction and very low emitter contact resistance.

Double-pulsed high-power excimer laser annealing is investigated for use as a means of implanted dopant activation. The laser setup incorporates two lasers that allow double pulse laser annealing with pulse offsets much smaller than the repetition of the individual XeCl excimer lasers. In this configuration, the pulse offset can be fine tuned. Sheet resistances are measured and thermal simulations are conducted to study temperature profiles. Results show, that the total laser energy needed for a complete activation increases with the pulse separation. The increase can be compensated by substrate heating. In this way the thermal budget can be tuned with more freedom.

This paper reviews the applications and potentials of back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) particularly for RF and microwave silicon-device-design enhancement. This type of SOG process gives direct access to the part of the device that is usually connected via the bulk Si, by allowing advanced patterning and contacting of the backside of the wafer (back-wafer) with respect to the front of the wafer (front-wafer). In this manner the resistive and capacitive parasitics of the device itself, which in silicon often inhibit high-frequency (HF) performance, can be reduced to a minimum. At the same time new device concepts are made possible. Examples of fabricated devices (varactor diodes, vertical double-diffused MOSFETs (VDMOSFETs) and complementary bipolar transistors) are given and described in relationship to issues such as the very limited thermal budget permitted in the back-wafer processing and the inherently high thermal resistance of the SOG devices

Silicon-on-glass vertical NPN's and PNP's with collector contacts on the back of the wafer directly under the emitter are investigated in relationship to the collector contacting method. Increased base-leakage and impact-ionization currents were found when the collector contacts were implanted. This effect is related to the residual implantation damage at a distance from the contact that cannot be thermal annealed during the low-temperature back-wafer processing

Sub-50 nm junction depth p+n and n+p diodes are formed by excimer laser annealing (ELA) of BF2 + and As+ implants, respectively, performed directly in the contact windows. The latter are etched through a stack composed of a reflective Al masking layer deposited on a silicon oxide isolation layer. The etching process, the laser anneal energy and the implantation parameters are optimized for low surface roughness at the silicon surface of the contact with respect to the final junction depth and good edge coverage of the diodes. In this manner near-ideal diode characteristics with ideality factors of 1.06-1.16 and low contact resistances are achieved in the laser energy processing window of 800-1000 mJ/cm2 . Moreover, the uniformity and reproducibility over the wafer is excellent

Ultrashallow junctions (USJ) were created by tilted 5 keV As+ implantation to a dose of 3x1015 cm−2 followed by excimer laser annealing (ELA). Sheet resistance and capacitances were measured in the background layer below the USJ. Results showed that sheet resistance was dependent on the laser energies in the close vicinity of these diodes. Doping profiles extracted from the capacitances indicated electrical deactivation here caused by the residual implantation defects. The extent and location of the residual damage is shown to be strongly dependent on the implantation dose and tilt angles, and also influenced by the laser annealing.

A set of circular ring-gate JFET test structures has been designed with which differential measurements can be utilized to electrically investigate the residual defects after the ELA (Excimer Laser Annealing) of implanted shallow junctions. The implanted ELA junction forms the top gate of the JFET and the diode I-V characteristics, sheet resistance and capacitance of the laterally uniform region below this gate, as well as the characteristics of the underlying pn junction formed between the bottom-gate and the source-channel-drain region can be determined. The measurements are used to evaluate the influence of various implantation parameters and laser energies on the residual defects associated with the shallow junction formation.

For backend processes, thermo-mechanical failure is one of the major failure modes. A representative metal structure in a Cu/low-k dual damascene process is examined considering the major thermal loads and process steps through combined finite element simulation with experiments. Firstly the low-k material, in our case the polymeric material SiLK (trade name of the DOW Chemical Company), is characterized and modeled to provide a reliable material model and data for the simulations. The coefficients for a Maxwell relaxation model are calculated, temperature dependency and its influence on the modulus are examined and the WLF coefficients are calculated providing time and temperature dependent material parameters for the process simulations. The main dual damascene process steps are simulated using the obtained material model. Stresses are examined at different critical locations. Furthermore an initial defect is placed at a low-k-oxide interface, where energy release rates are determined. Our results show that Cu/low-k structures exhibit significantly different reliability characteristics than their aluminum predecessors, are more critical from several design aspects. This not only makes the stress management in the stacks more difficult, but also strongly impact packaging.

SiLK [I] semiconductor dielecvic is a polymeric material developed for use as a thin film dielectric in the interconnect structure of high density integrated circuits. Among others, its thermo-mechanical properties play a dominant role for the integrity and reliability of the interconnect, during processing, testing and use. Being a polymer, SiLK films may show viscoelastic (time-dependent) behavior. In this paper, we use nano-indentation experiments to determine the viscoelastic properties of a thin SiLK film on a silicon substrate as a function of temperature within the range 25-100”C. Also, the effect of the degree of curing of the films on the viscoelastic properties is studied. The experiments indeed show that the SiLK film responds in a viscoelastic way. The viscoelastic behavior can be described by a linear viscoelastic generalized Maxwell model with a power law relaxation spechum. The effect of temperature can be modeled by an Arrhenius timetemperature superposition in the temperature range 25-10O0C. Thus, we obtain a full description of the viscoelastic properties of the SiLK film that can he directly implemented in a (commercially available) Finite Element Modeling package lie Marc or Ansys. Furthermore, the degree of curing of the SiLK film clearly affects the viscoelastic properties. Within the range of cure index from 0.65 to 0.98, a significant change in the relaxation modulus is observed.

For backend processes, thermo-mechanical failure is one of the major failure modes. A representative metal structure in a Cu/low-k dual damascene process is examined, considering the major thermal loads and process steps through combined finite element simulation with experiments. Firstly, the low-k material, in our case the polymeric material SiLK (trade name of the Dow Chemical Company) is characterized and modeled to provide a reliable material model and data for the simulations. Characterization measurements (nano-indentation-creep test) are carried out on a polymer film deposited on a substrate. Here a quasi-elastic approach is used to account for the substrate influence and the time dependency acting at the same time. Elastic indentation curves are simulated with a varying modulus of the film within an expected interval. The coefficients for a Maxwell relaxation model are calculated, and verified through FEM simulations. Furthermore results of temperature dependency and influence on the modulus are examined and the WLF coefficients are calculated providing time and temperature dependent material parameters for the process simulations. The main dual damascene process steps are simulated using the obtained material model. Stresses are examined at different critical locations. Furthermore an initial defect is placed at a low-k-oxide interface, where energy release rates are determined. Our results show that Cu/low-k structures exhibit significantly different reliability characteristics than their aluminum predecessors, which are more critical from several design aspects. This not only makes the stress management in the stacks more difficult, but also strongly impacts packaging.

The effect of equal channel angular pressing on the microstructure of copper samples was studied by X-ray line profile analysis. Pure Cu samples were processed by equal channel angular pressing with 3 passes in route A. Samples were taken from the vicinity of the channel intersection, and along a profile across the deformation zone, microhardness and XRD measurements were performed. For the high resolution line profile analysis of the diffraction spectra, convolutional-multiple-whole-profile CMWP method was applied, dislocation density and grain size were calculated, furthermore the density of twin boundaries were determined. Results show a rearrangement in the dislocations in the third pass leading to a rise in the density of twin boundaries.