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Air gap (AG) interconnects, with an ideal dielectric constant k of 1, is a promising approach to reduce signal propagation delay. In this paper, a comparative study of AG and dielectric copper damascene interconnect structures is performed through Raphael™ electric field simulation to investigate the capacitance benefit of introducing AG when scaling to small dimensions. The variation in total capacitance as a function of half pitch is simulated for different AG integration schemes proposed in the literature. Ideal and practical cases of these different integration schemes are simulated and compared to assess whether interconnect structures using a low- k ( k = 2.3) dielectric are more suitable than AG interconnects at scaled dimensions. The effect of using an additional (SiC-based) stiff liner on the AG capacitance benefit is also investigated. Finally, we verify our simulations using sub-40 nm half pitch AG structures prepared using the conformal and non-conformal processes.

In this work we integrate an advanced k=2.3 spin-on polymer at 40nm ½ pitch. K-value restoration techniques are investigated and complete k-value restoration is demonstrated using an in-situ HeH 2 plasma. An EUV compatible stack and a dielectric dual hard mask scheme is developed to pattern trenches with good uniformity and low litho-etch bias. The impact of scaling the dielectric spacing and of direct CMP on time dependent dielectric breakdown is also studied.

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.

Key features of the RIM-13 EUV actinic reticle imaging microscope are summarised. This is a tool which generates aerial images from blank or patterned EUV masks, emulating the illumination and projection optics of an exposure tool. Such images of mask defects, acquired by a CCD camera, are analysed using the tool software to predict their effect on resist exposure. Optical, mechanical and software performance of the tool are reported.

Key features are presented of the RIM-13 reticle imaging microscope developed for actinic aerial image monitoring of blank and patterned EUV reticles. Details of the opto-mechanical design, module layout, major subsystems including the EUV source and performance of the tool are presented.

Key features are presented of two high-resolution EUV imaging tools: the MS-13 Microstepper wafer exposure and the RIM-13 reticle imaging microscope. The MS-13 has been developed for EUV resist testing and technology evaluation at the 32nm node and beyond, while the RIM-13 is designed for actinic aerial image monitoring of blank and patterned EUV reticles. Details of the design architecture, module layout, major subsystems and performance are presented for both tools.

Key features are presented of the Exitech MS-13 EUV Microstepper tool developed for EUV resist testing & technology evaluation at the 32nm node and beyond. Details of the tool design architecture, module layout, vacuum chamber, major subsystems including source, optics and performance specifications are given.

A strong demand exists for techniques that extend application of ArF immersion lithography. Besides techniques such as litho-friendly design, dual exposure/patterning schemes, customized illumination, alternative processing schemes are also viable candidates. One of the most promising alternative flows uses image reversal by means of a negative tone development (NTD) step with a Fujifilm solvent-based developer. Traditionally, contact and trench printing uses a dark-field mask in combination with positive tone resist and positive tone development. With NTD, the same features are printed in positive resist using light-field masks, and consequently with better image contrast. We present an overview of NTD applications, comparing the NTD performance to that of the traditional development. Experimental work is performed at a 1.35 numerical aperture, targeting the contact/metal layers of the 32- and 22-nm nodes. For contact printing, we consider both single- and dual-exposure schemes for regular arrays and 2-D patterns. For trench printing, we study 1-D, line end, and 2-D patterns. We also assess the etch capability and critical dimension uniformity performance of the NTD process. We proves the added value of NTD. It enables us to achieve a broader pitch range and/or smaller litho targets, which makes NTD attractive for the most advanced lithography applications, including double patterning.