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Designing high-performance integrated circuits that balance area, speed, and power is increasingly challenging. This study optimises hardware implementation of FIR filters using an innovative Amalgam Multiplier, minimising resource use without compromising performance. The key challenge in designing signal processing hardware is the multiplier design, which significantly affects efficiency. This study explores integrated circuit optimisation, addressing the delicate balance between area utilisation, speed, and power consumption. Focusing on hardware implementation of Finite Impulse Response (FIR) filters in signal processing, the article starts with a conventional FIR filter design using a standard array multiplier which consumed 1.790 W, with 8 s real-time completion. Then, Linear Phase FIR (LP-FIR) filter is designed using Braun and Dadda Multiplier. LP-FIR filter with Braun multiplier consumed 1.436 W power and 26 s of completion time whereas LP-FIR with Dadda multiplier consumed 1.363 W power and 23 s of completion time. Finally, the implementation of novel LP-FIR enhanced by Amalgam multiplier consumed 0.302 W power and 10.29 s of completion time, marking a significant advancement in integrated circuit design. [ABSTRACT FROM AUTHOR]

The Hilbert transformation for generating the analytic signal or signal envelope is widely used in modern communication receivers, in radar and sonar systems. It introduces a 90 ∘ phase shift of the input signal. Since the impulse response of the ideal Hilbert transformer is non-causal, it must be approximated by an FIR or IIR filter. This paper shows results of novel algorithms for designing broadband digital IIR Hilbert transformers and its implementation. The designs employ Galerkin or collocation techniques. The transfer function of the Hilbert transformer is a rational polynomial of low order and exhibits approximately linear phase. The filters match the 90 ∘ phase shift requirement of Hilbert transformers almost perfectly and exhibit approximately constant group delay in the passband. The achieved image rejection ratio is typically larger than 50 dB. The quantization of the filter coefficients is realized by a Canonical Signed Digit (CSD) representation, reducing the hardware resources compared with two's complement. The resulting filters are multiplier-less, which is crucial for high-speed signal processing and low power consumption. The design techniques and the CSD representation are realized in a MATLAB toolbox. The filters were moreover implemented in VHDL and SystemC. Additionally, a MATLAB tool for automatically generating a VHDL package containing the filter parameters has been implemented. [ABSTRACT FROM AUTHOR]

Parallel scan architecture and RFID-based Anti-Collision Enabled Robot Processor can significantly enhance safety and efficiency in the manufacturing industry by using RFID technology to prevent collisions and improve the navigation of robots within the workspace. One such application is in robot navigation, where it can play a crucial role in enabling collision avoidance in multi-robot environments. In our recent work, we have proposed and developed a novel processor that incorporates a smart algorithm designed specifically to address the issue of collisions among multiple robots operating in the same workspace. By leveraging Parallel scan architecture and RFID technology, we have successfully created a system that can efficiently avoid both self-collisions between robots and collisions with physical objects. The implementation of our processor was achieved using VHDL, a hardware description language. Through careful design and simulation, demonstrated the feasibility and effectiveness of the approach. The successful synthesis of the proposed design has enabled to obtain the RTL schematic view of the processor, bringing one step closer to realizing a practical and effective Parallel scan architecture and RFID-based collision avoidance system for multi-robot environments. This work has the potential to significantly improve the safety and efficiency of robot operations in complex and dynamic settings. The Parallel scan architecture and RFID system can also provide valuable data for process analysis and optimization, contributing to continuous improvement in the manufacturing process. [ABSTRACT FROM AUTHOR]

CABAC (Context-based Adaptive Binary Arithmetic Coding) is a single operation mode for entropy coding in the two last video coding standards VVC (Versatile Video Coding) and HEVC (high-efficiency video coding). Otherwise, the CABAC+ used in VVC have been improved and partially changed compared to that used in HEVC. For high-resolution applications, the pick of one bin/cycle is not sufficient and it is a very challenging task to implement pipeline, parallel and mixed CABAC decoding architecture by simply adding more stages due to the data dependencies which and cause it to be the throughput bottleneck for video decoding. Mainly, the CABAC decoder is based on three stages: CSM (Context Selection and Modeling), BAD (Binary Arithmetic Decoding) and DBZ (De-binarization). Where the CSM and BAD adopted in CABAC VVC are changed compared to that used in CABAC HEVC. Consequently, in order to improve the CABAC decoder throughput with good area cost, new mixed design of CABAC MxVH_CABAC on a FPGA is proposed that can be support the SEs (syntax elements) in two recent standards VVC and HEVC respectively. This work is designed, described in VHDL language and implemented on FPGA Virtex-7. As result, the throughput is improved in our mixed design MxVH_CABAC and ranging between 166.33 Mbins/s and 665.32 Mbins/s with gain in area cost equal to 17.24% compared to those consumed in the both proposed designs CABAC_HEVC and CABAC_VVC. Additionally, the efficiency of MxVH_CABAC is about 0.069 Mbins/s/LUTs and it is better than those obtained in the other works in literature. [ABSTRACT FROM AUTHOR]

La investigación tiene como objetivo desarrollar una teoría de aplicabilidad del operador matemático de convolución, como modelador de sistemas físicos. El método comprende un análisis de compatibilidad entre el modelo matemático y las etapas del sistema, interpretando el significado de los componentes y las variables físicas. Se obtiene como resultado una matriz de soporte, para el abordaje de investigación, mantenimiento y optimización de sistemas, a través de un laboratorio móvil de arreglos de cometas proyectivas, para identificación de patrones y desarrollo de tecnología en el área de mitigación de impacto en parques de energías renovables, lo que permite aportar una técnica de configuración dinámica de parámetros del modelo.

In this paper, we present a novel DILTS algorithm that uses a new approach inspired by the energy efficiency of dragonflies. The algorithm optimizes the energy-harvesting mechanisms in IoT devices, inspired by the way dragonflies use wind energy to fly. A sophisticated algorithm optimizes power consumption during task execution, saving energy and speeding up tasks while maintaining the application throughput. The algorithm leverages lazy task scheduling (LTS) to enhance task execution performance. The proposed algorithm evaluates the energy levels of each task and implements an LTS method. This LTS approach improves performance and task management by streamlining scheduling data and reducing overhead. The LTS model reliably optimizes the energy across microbenchmarks and real-time IoT devices. To assess the efficiency and practicality of our algorithm, we compared it to four alternatives. Our novel algorithm outperformed the others with a chip area of 856 μm2, performance speed of 7.11 ns, scheduling accuracy of 94%, and response time of 2.61 ns. Our simulations showed that our proposed method reduced energy consumption by up to 10.02% compared to existing methods. We evaluated the performance of the algorithms on a Zynq 7000 FPGA using the Xilinx Vivado platform via simulations. Our novel algorithm can improve the energy efficiency of green data centers. [ABSTRACT FROM AUTHOR]

Encryption algorithms work with very large key values to provide higher security. In order to process high-capacity data in real-time, we need advanced hardware structures. Today, when compared to the previous designing methods, the required hardware solutions can be designed more easily by using Field Programmable Gate Array (FPGA). Over the past decade, FPGA speeds, capacities, and design tools have been improved. Thus, the hardware that can process data with high capacity can be designed and produced with lower costs. The purpose of this study is to create the components of a high-speed arithmetic unit that can process high-capacity data, which can also be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed and high-capacity adders that constitute high-speed multiplier and look-up tables were designed by using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. The simulation results were obtained through ModelSIM and ISIM programs.

Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed. [ABSTRACT FROM AUTHOR]

Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA. [ABSTRACT FROM AUTHOR]

An FPGA based alarm system, available of using unlimited number of inputs was programmed and put in use, in this work. A low cost FPGA RZ Easy A 2.2 was used, with its four dip or button switches acting as inputs. As soon as one or more switches are ON (bit 1), the respective LED lights on, while at the same time, seven segment display shows the number of ON state inputs, corresponding, for example, to the opened doors of a house. Simultaneously the buzzer clock algorithm is activated leading buzzer to sound. If all switches go manually to OFF state (bit 0), then all LEDs are off, buzzer stops sounding and seven segment display shows zero, thus indicating for example, that no house entries are open. The above function resembles a finite state machine, since the output state, depends on the inputs of the system. The VHDL code of our system gives the opportunity of having no limitation on the number of inputs and also the ability of changing the ringing rate of the buzzer. [ABSTRACT FROM AUTHOR]

Modular arithmetic is often used to create high-speed computing systems based on both custom digital VLSI circuits and field-programmable gate arrays (FPGAs). The problems of hardware implementation of neural networks based on modular arithmetic calculations are relevant today. In this study, the problem of implementing modular adders in the library for designing custom CMOS VLSI systems and FPGAs is considered. Systems of both fully and incompletely defined (partial) Boolean functions, as well as algorithmic descriptions in the VHDL language, are used as the initial descriptions of modular adders. Logical optimization preceding logical synthesis is carried out in the class of disjunctive normal forms, Reed–Muller polynomial representations, and representations of Boolean function systems by binary decision diagrams. Nine experiments are carried out on the efficiency of applying logic optimization in the circuit implementation of modular adders in the library for designing custom CMOS VLSI circuits and FPGAs. The obtained circuits of modular adders for CMOS VLSI systems are estimated by area (total number of transistors), delay, and power consumption; and for FPGAs, by the number of programmable logic elements and power consumption. The experimental results show that the use of partial function models and preliminary logical optimization based on binary decision diagrams makes it possible to obtain modular adders characterized by lower delay values. Algorithmic VHDL models make it possible to obtain CMOS modular adder circuits with a smaller area and lower power consumption. [ABSTRACT FROM AUTHOR]

High-Efficiency Video Coding (HEVC) has become popular according to its excellent coding performance, in particular in the case of high-resolution video applications. However, the significant gain in performance is accompanied by a higher encoding complexity compared to the H.264/AVC standard. The motion estimation (ME) is the most time-consuming part that removes temporal redundancy. To reduce the motion estimation complexity, many fast algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. This paper presents a design for the fast ME algorithm with a variable block size of HEVC standard which is the "TZ search". The design is described in VHDL language and synthesized to Altera Stratix III FPGA. The hardware architecture throughput reaches a processing rate up to 78 million pixels per second at 100 MHz. For the validation proposed design, an IP core is presented using the embedded video system on a programmable chip (SoPC). Finally, compared to other designs existing in the literature, the proposed architecture shows more efficiency in terms of hardware cost and improved performance. This design can be used in ultra-high-definition real-time TV coding (UHD) applications. [ABSTRACT FROM AUTHOR]

Encryption algorithms work with very large key values to provide higher security. To process high-capacity data in real time, we need advanced hardware structures. Today, compared to previous design methods, hardware solutions can be designed more easily using Field-Programmable Gate Arrays (FPGAs). Over the past decade, FPGA speeds, capacities, and design tools have been improving. Thus, the hardware that can process high-capacity data can be designed and produced with lower costs. This study aims to create the components of a high-speed arithmetic unit that can process high-capacity data and be used for FPGA encoding algorithms. In this study, multiplication algorithms were analyzed. High-capacity adders that constitute high-speed multiplier and look-up tables were designed using Very High-Speed Integrated Circuit Hardware Description Language (VHDL). The designed circuit/multiplier was synthesized with ISE Design Suite 14.7 software. Simulation results were obtained using the ModelSIM and ISIM programs. [ABSTRACT FROM AUTHOR]

Self-organizing map (SOM) is a type of artificial neural network that provides a nonlinear mapping from a given high-dimensional input space to a low-dimensional map of neurons for clustering. The clustering of high-dimensional vectors is too slow for SOM when implemented in software. In such cases, an application-specific hardware SOM accelerator is highly desirable. Field-programmable gate array (FPGA) implementation is a popular platform to implement hardware SOM. In our previous work, a nested hardware SOM architecture, which has a homogeneous modular structure to enhance expandability, was proposed. This paper investigates the impact of the nested hardware SOM on FPGA implementation tools that perform logic synthesis, place, and route (PAR). Experiments revealed that the nested architecture provided better results in resource usage and performance. FPGA resource usage of the nested architecture was 97.2% of that of the flat design on average. Importantly, the nested architecture operated at 10% higher clock frequencies compared to flat SOM designs. In addition, the pipeline computation was improved by increasing the pipeline stages so that it operates with a higher clock frequency. The operable clock frequency was 81 MHz, which was 21 MHz higher than its predecessor. [ABSTRACT FROM AUTHOR]

Polar codes are a class of block codes which are widely used in communication networks. Polar codes have been utilized in the fifth generation of enhanced mobile broadband systems (5G) due to their performance in error correction and also their low instinct complexity in implementation. However when they come in very large blocks, their efficient implementation in reasonable time is challenging. The automatic code generator (ACG) tools are useful and essential in these cases, when the design process should be error prone and time consuming. This paper presents an error prone and fast ACG tool to generate the VHDL description code at gate level for Polar decoders in multimedia communication systems according to user adjusted parameters including code-length, code-rate and quantization width, called PoCH tool. The PoCH constructs the Polar decoder using the design SNR and Bhattacharyya parameters which are set by the user, or are provided by a file consisting of the frozen bits location. The PoCH can generate the Polar decoder for four famous algorithms including SC, SSC, Fast-SSC and Fast-SSC + BiREP algorithms. To validate the performance of the PoCH tool, the block counts is presented for each generated code for various code-length, code-rate and Bhattacharyya parameters. Finally, the time consumed by the tool to generate Polar channel decoders for each algorithm is compared. [ABSTRACT FROM AUTHOR]

An Instructional Processor has been developed as a design example in an Advanced Digital Systems course. The architecture is modelled in VHDL and can be simulated using Xilinx design tools. A basic microcontroller is created by adding memory-mapped input/output (I/O). The hardware system can be synthesized and implemented on a field programmable gate array (FPGA). The goal of this project was to add serial communication capabilities via software and a hardware UART (universal asynchronous receiver transmitter). The design allows direct access to the UART data registers (receive and transmit), status register (flags), and control register (baud rate). Test programs, written in assembly language, were used to verify the communication protocol and timing via VHDL simulation. The FPGA microcontroller was able to communicate with serial devices at various baud rates. The UART gives students an in-depth look at both the internal details and external interfacing of a real-life system. [ABSTRACT FROM AUTHOR]

Hardware/software co-simulation is a technique that can help design and validate digital circuits controlled by embedded processors. Co-simulation has largely been applied to system-level models, and tools for SystemC or SystemVerilog are readily available, but they are either not compatible or very cumbersome to use with VHDL, the most commonly used language for FPGA design. This paper presents a direct, simple-to-use solution to co-simulate a VHDL design together with the firmware (FW) that controls it. It aims to bring the power of co-simulation to every digital designer, so it uses open-source tools, and the developed code is also open. A small patch applied to the QEMU emulator allows it to communicate with a custom-written VHDL module that exposes a CPU bus to the digital design, controlled by the FW emulated in QEMU. No changes to FW code or VHDL device code are required: with our approach, it is possible to co-simulate the very same code base that would then be implemented into an FPGA, enabling debugging, verification, and tracing capabilities that would not be possible even with the real hardware. [ABSTRACT FROM AUTHOR]

This letter presents a novel leading zero counter (LZC) able to efficiently exploits the hardware resources available within state-of-the-art FPGA devices to achieve high-speed performances with limited energy consumption. Post-implementation results, obtained for operands bit-widths varying between 4- and 64-bit, demonstrate that the new design improves its direct competitors in terms of occupied lookup tables (LUTs), power consumption, and computational speed. As an example, when implemented using the Xilinx Artix-7 xc7a100tcsg324 device, the new 64-bit LZC utilizes up to 36% less LUTs, dissipates up to 2.8 times lower power and is up to 20% faster than state-of-the-art counterparts. [ABSTRACT FROM AUTHOR]

The problems of synthesis of combinational circuits of code converters designed to reduce the length of words from a given set of encoded binary words is considered. The encoding assumes that different binary words will be encoded by different binary codes of shorter length. Code converters of this type are designed to reduce the length of binary words transmitted in digital systems over data buses when the bit depth of the transmitted words exceeds the bit depth of the data bus. For example, 18-bit or 17-bit words need to be transmitted over a 16-bit data bus. Each such word can be transmitted in two cycles of operation of a digital system; however, this approach reduces the overall performance of the system. One of the approaches to solve such problems is the development of combinational circuits that convert long binary encoded words into shorter ones. The proposed methods for solving the problem of synthesizing circuits of code converters are based on the compilation and logical minimization of such forms of systems of incompletely specified Boolean functions as disjunctive normal forms (DNFs) and binary decision diagrams called BDD representations. Using BDDs to minimize representations of k-valued functions that depend on Boolean variables is also proposed. Technology-independent logical minimization of functional descriptions of the designed code converters is proposed to be performed by programs for minimizing the systems of Boolean functions in the DNF class and programs for joint minimization of BDD representations of systems of completely specified Boolean functions. Minimization of functional descriptions is aimed at reducing the hardware complexity of combinational circuits in the basis of library elements or FPGA elements implementing code converters of the class in question. [ABSTRACT FROM AUTHOR]

Binary decision diagram (BDD) is used for technology-independent optimization, performed as the first stage in the synthesis of logic circuits in the design of application-specific integrated circuits (ASICs). BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph is associated with the complete or reduced Shannon expansion formula. Binary decision diagrams with mutually inverse subfunctions (cofactors) are considered. We have developed algorithms for finding algebraic representations of cofactors of the same BDD level in the form of a disjunction or conjunction of other inverse or non-inverse cofactors of the same BDD level. The algorithms allow reducing the number of literals by replacing the Shannon expansion formulas of a system of Boolean functions. It is proposed to use the developed algorithms for an additional logic optimization of the constructed BDD representations of systems of Boolean functions. The experimental results of application of the corresponding programs in synthesizing the logic circuits in the design library of custom VLSI CMOS circuits are presented. [ABSTRACT FROM AUTHOR]

Digital filters are vital a part of digital signal process. The Finite impulse response (FIR) in various signal processing applications has been employed. It has wide range of applications such as image processing, data transmission, biomedical, wireless communication networks etc. The digital finite impulse response consists of three main blocks. They are multiplier, adder, and delay. FIR filter design causes excessive area and power consumption because of multiplications is of large number. Multiplier factor is the main block in FIR filter. Various ways are delineate within the study to execute application specific integrated circuit (ASIC) in digital finite impulse response filter. High power consumption in partial product generation of the standard multiplier factor section. In planned work, the implementation of Radix-4 Booth multiplier factor and improved booth has been performed for 16-Tap FIR filter. The multiplier factor design helps to reduce the amount of steps in multiplication and additionally in digital circuits decrease the propagation delay and the power consumption. Compared to FIR filter with traditional multiplier factor results clearly indicate that power and capacity are condensed. The results show that the improved Booth multiplier based FIR filter ends up in smallest power and space, for communication purpose and FIR filter is additionally applicable. [ABSTRACT FROM AUTHOR]

A Fuzzy Inference System (FIS) is a system that represents human reasoning based on fuzzy if-then rules to extract valid results from imprecise or uncertain information. These systems have been applied to various engineering fields, such as control and image recognition, and have encouraged the search for development tools that provide facilities for the design, simulation, and implementation of FISs. Most of the available software tools for the design of FISs have been developed by the scientific community, and very few are commercial tools. According to the state of the technology, the fuzzy systems implemented in hardware have shown higher performance than software implementations. For this reason, different strategies for automatic hardware synthesis of FISs have been proposed in the literature. The available tools for FIS implementation, including MATLAB, Simulink, and Xfuzzy environment, require advanced hardware knowledge, and it is necessary to synthesize and implement the program on FPGA each time a change is made to the code. This paper presents a novel approach for the implementation of fuzzy systems on hardware devices that enables the direct implementation of FISs through a graphical user interface. The VHDL code is pre-synthesized and integrated with the interface, allowing users to experiment with different input parameters, such as membership functions and fuzzy rules, without resynthesizing the code on an FPGA. To verify the effectiveness of the proposed approach, experiments were conducted on two similar System-on-Chip (SoC) devices, VEEK-MT and VEEK-MT2. The results showed that the proposed solution represents a significant advancement in the study of fuzzy systems on hardware devices, providing a flexible and user-friendly approach to their design and implementation. [ABSTRACT FROM AUTHOR]

In this letter, we present the design and implementation results of two hardware accelerators for the supersingular isogeny key encapsulation (SIKE) suite. These designs aim at enabling quantum-safe cryptography solutions for constrained platforms by offloading the cost of bulk arithmetic from the main processor. One of the proposed architectures has area reduction as the main implementation goal; the second design improves the former on the energy footprint. This software–hardware co-design addresses the challenges of performing bulk arithmetic in software and reducing the control complexity in hardware, thus minimizing the communication overheads found on simple arithmetic accelerators. Compared to other designs in the literature, the proposed architectures do not rely on in-fabric memory and processing units, a key point for porting such solutions to any implementation technology such as field-programmable gate arrays (FPGAs). [ABSTRACT FROM AUTHOR]

Hardware Trojans have concealed modifications to integrated circuits (ICs) that can alter their functions, performance, or security properties. Existing Trojan detection methods are designed primarily to detect Trojans at the gate-level IC abstraction and lower levels, and only a few studies have investigated Trojan detection at the register transfer level (RTL). This study presents a novel machine learning-based approach for RTL-level Trojan detection, which leverages conditional statements from Verilog/VHDL code as ML features. Our proposed method has several significant novelties. Firstly, it can detect unknown Trojan instances since we incorporate general features for all Verilog circuits. Second, our approach can detect nontrigger-based Trojans, which are a type of Trojan that is particularly challenging to detect and has not been addressed by many existing techniques. Third, we incorporate feature engineering techniques, including Mutual Information and Person-Coefficient Correlation, to select the best features. We also implement feature scaling with standardization before balancing the data set. Our experimental results demonstrate that our approach achieves an average accuracy of 95.65% in the detection of Trojans, which is higher than previous detection techniques. The method is tested in the Trust-Hub Trojan benchmark RTL design, which demonstrates its effectiveness in detecting a wider range of Trojans at the RTL level. In summary, our novel approach shows great promise for enhancing hardware security by detecting a wider range of Trojans, including previously unseen Trojans, and improving detection&Ahat; accuracy.

One of the languages available to describe a digital system in FPGA is the VHDL language. Since programming in hardware requires a different way of thinking than developing software, the students face some difficulties when trying to design in VHDL language with the previous and long experiences kept in mind in the learning of software imperative programming. These are its concurrency, parallel and sequential model. Due to the insufficient understanding of these topics, it is difficult for students to master the VHDL language. Analogies change the conceptual system of existing knowledge by linking the known to the unknown and by changing and strengthening their relationships. This study contributes to overcoming the problems that students encounter in the coding of the above-mentioned topics in VHDL language by using their experiences in traditional programming languages through analogies. Analogies were used in an undergraduate embedded systems course to explain complex concepts such as those related to signals, concurrent/parallel process; and to encourage comprehensive projects in digital circuit design. In feedback from students, the discussion and negotiation of analogies seems to minimize confusion and from using inappropriate expressions in using VHDL language.

This paper proposes a novel method for constructing optical zero-correlation zone (OZCZ) codes based on the Mutually Orthogonal Complementary Sets (MOCS) matrix and the concatenation operation. The most important property of the obtained codes is that the periodic correlation function of the proposed codes is zero for the phase shifts within the zero-correlation zone. The procedure of construction is simple, flexible and offers increasing number of users M = 2 n + 1 . In the other hand, we have presented a fully reconfigurable hardware implementation based on very high description language of the proposed OZCZ codes for optical code-division multiple-access encoder system. The implementation is performed on an Altera field-programmable gate arrays device using ROM memory and an up counter. The simulation results have been found satisfactory and are in conformity with the theoretical observations. [ABSTRACT FROM AUTHOR]

This paper proposes a microsystem based on the field programmable gate arrays (FPGA) electronic board. The preliminary objective is to manipulate a programming language to achieve a control part capable of controlling the speed of electric actuators, such as direct current (DC) motors. The method proposed in this work is to control the speed of the DC motor by a purely embedded architecture within the FPGA in order to reduce the space occupied by the circuit to a minimum and to ensure the reliability of the system. The implementation of this system allows the embedded MicroBlaze processor to be installed side by side with its memory blocks provided by Xilinx very high-speed integrated circuit (VHSIC) hardware description language (VHDL), Embedded C. The control signal of digital pulse-width modulation pulses is generated by an embedded block managed by the same processor. This potential application is demonstrated by experimental simulation on the Vertix5 FPGA chip. [ABSTRACT FROM AUTHOR]

Bit-pattern matching is an important technological capability, used in many fields such as network intrusion detection (NID) and packet classification systems. Essentially, it involves the matching of an input bit pattern to a bit-pattern entry of a memory structure inside the system. Contemporary methods focus on the decomposition of the input bit pattern into smaller and more manageable parts, with the subsequent parallel processing of these elements. This fragmentation promotes the use of advanced pipeline techniques and hardware optimizations, enabling these methods to achieve very high throughputs and reasonable efficiency. However, the functionality of their respective circuits is limited to only performing pattern matching when there is no interference. In this article, we intend to present a circuit that performs pattern matching under heavy interference; instead of fragmentation, a more holistic approach will be adopted. To improve the throughput of the circuit, long bit sequences will be directly compared to many memory entries simultaneously. The minimization of hardware consumption and maximization of efficiency in these comparisons will be achieved with the use of novel hardware architecture that is based on pipelined adder trees and comparators. The platform of implementation is an FPGA (Field-Programmable Gate Array). [ABSTRACT FROM AUTHOR]

This paper presents high-performance computing efforts with FPGA for the accelerated pulsar/transient search for the square kilometre array (SKA). Case studies are presented from within SKA and pathfinder telescopes highlighting future opportunities. It reviews the scenario that has shifted from offline processing of the radio telescope data to digitizing several hundreds/thousands of antenna outputs over huge bandwidths, forming several hundreds of beams, and processing the data in the SKA real-time pulsar search pipelines. A brief account of the different architectures of the accelerators, primarily, the new generation field programmable gate array-based accelerators, showing their critical roles to achieve high-performance computing and in handling the enormous data volume problems of the SKA is presented here. It also presents power-performance efficiency of this emerging technology and presents potential future scenarios. [ABSTRACT FROM AUTHOR]