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1. Enhanced FPGA linear phase FIR filter with amalgam multiplier.

2. Multiplier-less Broadband and Linear Phase Digital Hilbert Transformers.

3. Optimizing design and manufacturing processes with an effective algorithm using anti-collision enabled robot processor.

4. Design and FPGA implementation of mixed VVC/HEVC CABAC decoding.

5. e-KiteLab: INVESTIGACIÓN EN FÍSICA APLICADA PARA MANTENIMIENTO Y OPTIMIZACIÓN DE SISTEMAS DE ENERGÍAS RENOVABLES

6. Improving Reed Solomon (RS) Decoder Using Two Simultaneously Modified Blocks of Chien Search and Syndrome

7. Modeling and Simulation of a Vending Machine Through FSM Using VHDL

8. Calculation of the Sigmoid Activation Function in FPGA Using Rational Fractions

9. Toolset for the Development of a Power Driver with Arbitrary Current Waveform for a Permanent Magnet Synchronous Motor

14. Implementation of Projects Based on FPGA: Practical Applications

15. DILTS: Dragonfly-inspired lazy task scheduling algorithm for efficient energy consumption control in IoT applications.

16. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier

17. Low Power Embedded SoC Design.

18. FPGA based telecommand system for balloon-borne scientific payloads.

19. A Simple, Low Cost and Multiple Input Alarm System, Functioning as Finite State Machine (FSM), Using VHDL and FPGAs.

20. Circuit Implementation of Modular Adders in Custom CMOS VLSI and FPGA.

21. Hardware implementation and validation of the fast variable block size motion estimation architecture for HEVC Standard.

22. High-Capacity Data Processing with FPGA-Based Multiplication Algorithms and the Design of a High-Speed LUT Multiplier.

23. Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture.

24. Methodology for the Implementation of FPGA in Technological Applications

25. Interference Cancellation by Using Viterbi Algorithm for Space Base AIS System

28. PoCH: automatic HDL code generator tool for Polar channel coding decoders in multimedia communication systems.

29. Implementing Serial Communication for the Instructional Processor.

30. Open-Source HW/SW Co-Simulation Using QEMU and GHDL for VHDL-Based SoC Design.

31. Design of Leading Zero Counters on FPGAs.

32. Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words.

33. Experimental Study of Algorithms for Minimization of Binary Decision Diagrams Using Algebraic Representations of Cofactors.

34. Digital Filter Design: Novel Multiplier Realization.

35. Fuzzy Hardware Tool: An Adaptable Tool to Facilitate the Implementation of Fuzzy Inference Systems in Hardware.

36. Hardware Acceleration of SIKE on Low-End FPGAs.

37. Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features

40. Automatic Generation of Verified Concurrent Hardware Using VHDL

42. FPGA Implementation of Area-Efficient Binary Counter Using Xilinx IP Cores

45. Design of FPGA-Based QPP Interleaver for LTE/LTE-Advanced Application

46. Transfer of Analogies in Traditional Programming Languages to Teaching VHDL

47. FPGA Implementation of a Novel Construction of Optical Zero-Correlation Zone Codes for OCDMA Systems.

48. A microsystem design for controlling a DC motor by pulse width modulation using MicroBlaze soft-core.

49. High-Throughput Bit-Pattern Matching under Heavy Interference on FPGA.

50. High-performance computing for SKA transient search: Use of FPGA-based accelerators.

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