Search

To enhance the dynamic performance and robustness of the voltage control system of islanded microgrid inverters, a new control strategy combining integral sliding mode (ISM) control and composite nonlinear feedback (CNF) control is proposed. In ISM control, firstly, a new reaching law is designed to improve movement quality in the reaching phase by improving the power term and introducing the inverse tangent function. Then, to improve disturbance observation accuracy, a variable gain extended state observer is designed by improving the regulation mechanism of the state variables according to deviation control. Using the idea of variable damping, linear and nonlinear feedback are combined into CNF control. Specifically, linear feedback provides a small damping ratio for faster system response, while nonlinear feedback increases the damping ratio to improve steady‐state performance. Simulation results show that the integral sliding mode‐composite nonlinear feedback (ISM‐CNF) control strategy cam balances convergence speed and chattering better and achieves higher steady‐state accuracy than conventional strategies. Moreover, ISM‐CNF control has better robustness to reference voltage variations and disturbances caused by sudden load changes. Therefore, the ISM‐CNF control strategy can accomplish voltage control of islanded microgrid inverters quickly and steadily, effectively suppressing system disturbances and enhancing stability and power quality. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

Summary: Fluorescent optical fiber temperature sensors require accurate online temperature monitoring in hazardous environments with strong electromagnetic fields, high voltages, flammability, or explosiveness. This imposes stringent requirements on the temperature coefficient stability of the bandgap reference (BGR) circuit. To address these challenges, this paper proposes a high‐order curvature compensation bandgap reference (HCC_BGR) circuit fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS (BCD) process. A traditional first‐order bandgap reference (TRA_BGR) circuit is also fabricated for comparison. Experimental results demonstrate that the proposed HCC_BGR circuit generates a stable 1.22‐V reference voltage with a low‐temperature coefficient of 5.56 ppm/°C from −20°C to 85°C. Compared to the TRA_BGR circuit, the HCC_BGR reduces the temperature coefficient by 3.07 times. Furthermore, the low‐dropout regulator (LDO) using the proposed HCC_BGR exhibits excellent line sensitivity of 1.52%/V from 3.4 to 5 V. [ABSTRACT FROM AUTHOR]

Summary: A current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV. [ABSTRACT FROM AUTHOR]

Summary: The double‐line frequency ripple power exists inherently in single‐phase power converters. To address this problem, active power decoupling (APD) technique is widely used. It diverts the ripple power into a small energy storage element by introducing passive and active power devices. This inevitably involves more voltage and current sensors for corresponding control, which raises the cost while decreasing reliability and power density. In this paper, a Lyapunov‐based methodology is proposed to achieve APD control without adding any sensor. According to the designed controller laws, the practical decoupling capacitor voltage will converge to its reference. The decoupling voltage reference is given by taking into account buffering the double‐line frequency ripple power. Afterward, the robustness against parameter perturbations of the proposed method is discussed. Finally, the experimental results verify the feasibility of the proposed control strategy. [ABSTRACT FROM AUTHOR]

With the development of high-speed analog-to-digital converter (ADC)-based wireline receivers, the Mueller–Muller clock and data recovery (MM-CDR) circuit has garnered increasing attention. But in the design stage, evaluating the loop performance of MM-CDR circuits in ADC-based wireline receivers is challenging due to the absence of a linearized model for a Mueller–Muller phase detector (MMPD). In this paper, a linearized model of the MMPD is proposed by analyzing the output probability of the MMPD in different transition patterns with random jitter injection, and the model is combined with an entire MM-CDR system to analyze the performance of the MM-CDR loop. Analysis of the linearized model and corresponding simulations indicate that when the reference voltage level in the MMPD is set equal to the amplitude of the average crossing voltage at the intersection of 011 and 110 patterns, the MMPD can obtain the maximum gain, which is determined by jitter, and the jitter transfer function and jitter tolerance can achieve optimum performance. [ABSTRACT FROM AUTHOR]

A design methodology for a resistorless low-power two-in-one voltage and current reference source working in subthreshold and moderate regions is described. The presented novel universal reference voltage–current source was implemented in ten different designs for seven different CMOS technologies. Six versions of these designs were silicon-proven using four different CMOS technologies. The example of implementation in 130 nm technology provides a reference current of 5 µA and reference voltage of 800 mV at supply voltages ranging from 0.9 V to 2.0 V with a total current consumption of 15 µA. The proposed circuit occupies a 1200 µm2 chip area and achieves 280 and 118 ppm/°C for all process corners and temperature variation from −40 °C to 125 °C. The power supply rejection ratio of output IREF without any filtering capacitor at 100 Hz and 10 MHz is 128 dB and 100 dB, respectively. The equivalent output current noise in the bandwidth from 1 Hz to 10 MHz reaches 9.1 nARMS. [ABSTRACT FROM AUTHOR]

This article presents an innovative APISMC method applied to PVS, integrating the MPPT technique for a boost converter. The primary objective of this approach is to maximize the converter's output power while ensuring optimal operation in the face of varying environmental conditions such as solar irradiance and temperature, while dynamically adapting to variations in system parameters, as demonstrated by the obtained results. To achieve this, a RVO is employed to generate reference voltage and power. A PI controller calculates the reference current based on this power. The APISMC control modeling utilizes all its reference variables to synthesize the sliding surface and duty cycle for optimal boost converter control. Simulations conducted demonstrate superior performance in terms of stability, speed, and control of the converter compared to traditional MPPT algorithms. The main contributions of this article include an improvement in system robustness against irradiance variations, thanks to the integration of an adaptive algorithm and a PI controller within the SMC. Moreover, the proposed theoretical and practical framework enables rapid MPPT attainment by adjusting the duty cycle in real-time, optimizing maximum power extraction and ensuring stable regulation even under non-ideal conditions. [ABSTRACT FROM AUTHOR]

Power electronic converters are widely used in various fields of electrical equipment. Due to their fast dynamics and non-linear nature, controlling them requires dealing with various complexities. Therefore, having a well-designed, high-speed, and robust controller is critical to ensure the effective operation of these devices. In a DC-DC converter, steady-state performance with minimum error and fast dynamic response relies on controller design. This paper presents the design of a multi-stage PID controller with an N-filter combined with a one plus proportional derivative (1+PD) controller. This controller illustrates fast tracking reference voltage; additionally, it shows incredible results when the DC-DC converter operates in different modes. The parameters of the proposed controller are effectively determined using the golden eagle optimization (GEO) algorithm. Furthermore, a comprehensive comparison between the proposed controller, proportional–integral–derivative (PID), and fractional order PID (FOPID) controllers, as well as different metaheuristic optimization methods in various conditions, has been conducted to demonstrate the effectiveness of the proposed controller. The behavior of the closed-loop system under different conditions has been thoroughly investigated. The superior time and frequency domain characteristics of the closed-loop system with the PIDn(1+PD) controller highlight its superiority over other controllers. The demonstrated enhancements in settling time, voltage regulation accuracy, and transient response emphasize the potential applicability of the proposed control strategy in real-world power electronics systems, particularly in scenarios requiring high efficiency, stability, and dynamic performance. [ABSTRACT FROM AUTHOR]

ABSTRACT In low‐voltage applications using low‐Q LC filters, alias‐free capacitor voltage acquisition can be achieved, but synchronous capacitor voltage sampling under high‐Q filters used in high‐voltage applications in grid‐forming converters causes some degree of distortion and results in degradation of the power supply quality. And the inherent 1.5 sampling periods that delay in this approach limit the control bandwidth, reduce the stability region, and result in an inadequate time domain response. Despite these shortcomings, this approach is widely accepted in practice. The conclusion of this paper is that shifting the capacitor voltage sampling instant to 2 µs before the pulse width modulation (PWM) reference voltage update results in almost the same distortion as synchronous sampling. However, it can improve the dynamic performance of the system. A distortion‐acceptable univariate feedback voltage dual‐loop active damping control topology with much reduced computational delay is proposed, which is based on an internal active damping loop using a discrete lead compensator and a proportional resonance controller in the external voltage loop. [ABSTRACT FROM AUTHOR]

The step-down DC/DC converter is characterized by the parametric uncertainty of its model and its high sensitivity to external disturbances identified by variations in the input voltage, load and output reference voltage. To overcome these limitations, this paper proposes the experimental evaluation of a new adaptive synergetic control law based on the M5P model tree for efficient output voltage control of the step-down type DC/DC converter. A combination of the synergetic technique, the fuzzy logic theory and the machine learning has been used for the first time to develop this advanced control law. The synergetic strategy is exploited to overcome the chattering problem arising from the use of the sliding mode approach which has been applied in previous research. Furthermore, the novel machine learning M5P tree-based approximator was designed and applied to approximate the unknown and imprecise dynamics of the studied converter. The learning data comes from the smart approximator, which is based on fuzzy logic, with the aim of extracting its own advantages and offering them to the new tree-based approximator M5P. This action will make it possible to improve the operation of the fuzzy approximator, which has already been studied in some research. Finally, the developed control strategy was successfully evaluated in the laboratory using the dSPACE 1104 board and compared with the fuzzy adaptive synergetic approach under different conditions of load variations and imposed references. The practical results show that the proposed tree adaptive synergetic approach is competitive with the fuzzy adaptive strategy in terms of ease of practical implementation, fast control execution and better output voltage regulation quality. [ABSTRACT FROM AUTHOR]

Summary: In the first part of this paper, we closely examine well‐known methods for balancing the output power level of the pseudo‐differential current‐reuse voltage‐controlled oscillator. We scrutinize their effectiveness in terms of canceling output mismatches, insensitivity to process, voltage, and temperature variations, and their capability of not degrading phase noise performance. Through analyses and simulations, it is shown that contrary to common belief, some techniques are not as effective as previously thought and should be employed only under specific circumstances. The best conventional approach is proven to be the use of a common‐mode shunting capacitor at the inductor's center tap node to create a virtual ground. In the second part, it is demonstrated that the current‐reuse voltage‐controlled oscillator can intrinsically produce balanced outputs without using any additional techniques or extra passive or active components. Using single‐ended tank capacitors instead of differential ones, the common‐mode voltage of the outputs is shunted to the real ground. This technique reintroduces a reference voltage to the tank circuit, forcing the oscillator to achieve equilibrium between positive and negative swings. The proposed current‐reuse oscillator is designed and post‐layout simulated in a 65‐nm CMOS process, covering a frequency range of 4.84–6.38 GHz with an average power consumption of 0.65 mW. It produces balanced outputs with an amplitude error of less than ±0.2% and achieves a phase noise of −126.7 dBc/Hz and FoMT of 201.8 dB at a 3‐MHz offset frequency. [ABSTRACT FROM AUTHOR]

Background and purpose: Magnetic resonance imaging (MRI) scanners are a major contributor to greenhouse gas emissions from the healthcare sector, and efforts to improve energy efficiency and reduce energy consumption rely on quantification of the characteristics of energy consumption. The purpose of this work was to develop a semi‐automatic analytical methodology for the characterization of the energy consumption of MRI systems using only the load duration curve (LDC). LDCs are a fundamental tool used across various fields to analyze and understand the behavior of loads over time. Methods: An electric current transformer sensor and data logger were installed on two 3T MRI scanners from two vendors, termed M1 (outpatient scanner) and M2 (inpatient/emergency scanner). Data was collected for 1 month (7/11/2023 to 8/11/2023). Active power was calculated, assuming a balanced three‐phase system, using the average current measured across all three phases, a 480 V reference voltage for both machines, and vendor‐provided power factors. An LDC was constructed for each system by sorting the active power values in descending order and computing the cumulative time (in units of percentage) for each data point. The first derivative of the LDC was then computed (LDC'), smoothed by convolution with a window function (sLDC'), and used to detect transitions between different system modes including (in descending power levels): scan, prepared‐to‐scan, idle, low‐power, and off. The final, segmented LDC was used to measure time (% total time), total energy (kWh), and mean power (kW) for each system mode on both scanners. The method was validated by comparing mean power values, computed using the segmented 1‐month LDC, for each nonproductive system mode (i.e., prepared‐to‐scan, idle, lower‐power, and off) against power levels measured after a deliberate system shutdown was performed for each scanner (1 day worth of data). Results: The validation revealed differences in mean power values <1.4% for all nonproductive modes and both scanners. In the scan system mode, the mean power values ranged from 29.8 to 37.2 kW and the total energy consumed for 1 month ranged from 11 106 to 14 466 kWh depending on the scanner. Over the course of 1 month, the portion of time the scanners were in nonproductive modes ranged from 76% to 80% across scanners and the nonproductive energy consumption ranged from 8010 to 6722 kWh depending on the scanner. The M1 (outpatient) scanner consumed 99.9 and 183.9 kWh/day in idle mode for weekdays and weekends, respectively, because the scanner spent 23% more time proportionally in idle mode on the weekends. Conclusions: A semi‐automatic method for quantifying energy consumption characteristics of MRI scanners was introduced and validated. This method is relatively simple to implement as it requires only power data from the scanners and avoids the technical challenges associated with extracting and processing scanner log files. The methodology enables quantitative evaluation of the power, time, and energy characteristics of MRI scanners in scan and nonproductive system modes, providing baseline data and the capability of identifying potential opportunities for enhancing the energy efficiency of MRI scanners. [ABSTRACT FROM AUTHOR]

The paper reports simple yet effective circuits for realizing XOR and XNOR logic operations with polarity, each employing a single current conveyor. The proposed polar logic circuits require four MOS switches and two resistors, besides a single CCII+ (second generation current conveyor), in each case. The new proposed circuits are simulated using 0.18 µm CMOS process parameters with a ± 1.8 V supply voltage and reference DC voltage of 1 V, thus enabling polar logic outputs. The polar output for logic 0 and 1 is in form of − 1 V and + 1 V respectively. The results included in support of the work are promising for future applications of the proposal in design of communication circuits. To facilitate better integration prospects, the proposed circuits are further simplified by removing one of the two used resistors and replacing CCII by CCCII (current controlled current conveyor). The simplified polar XOR gate is also verified through simulations. System design applications are expected to evolve from proposed work. The new proposed circuits are expected to significantly contribute to the advancement of circuit design. [ABSTRACT FROM AUTHOR]

Multi-level inverters have characteristics suitable for high-voltage and high-power applications through various topology configurations. These reduce harmonic distortion and improve the quality of the output waveform by generating a multi-level output voltage waveform. In particular, an active neutral-point-clamped topology is one of the multi-level inverters advantageous for high-power and medium-voltage applications. It has the advantage of controlling the output waveform more precisely by actively clamping the neutral point using an active switch and diode. However, it has a problem, which is that an unwanted zero-crossing current may occur if an inaccurate switching signal is applied at the time when the polarity of the output voltage changes. In this paper, a control strategy to suppress the zero-crossing current of a single-phase half-bridge three-level active neutral-point-clamped inverter is proposed. The operating principle of a single-phase half-bridge three-level active neutral-point-clamped inverter is identified through an operation mode analysis. In addition, how the switching signal is reflected in an actual digital signal processor is analyzed to determine the situation in which the zero-crossing current occurs. Through this, a control strategy capable of suppressing zero-crossing current is designed. The proposed method prevents a zero-crossing current by appropriately modifying the update timing of reference voltages at the point where the polarity of the output changes. The validity of the proposed method is verified through simulation and experiments. Based on the proposed method, the total harmonic distortion of the output current is significantly reduced from 12.15% to 4.59% in a full-load situation. [ABSTRACT FROM AUTHOR]

Multilevel inverters with improved voltage quality are widely used in applications such as motor control and electric vehicles. The four-level active neutral point clamped (4L-ANPC) inverter effectively meets the demands for high power density and low device voltage stress. However, balancing the capacitor voltage and reducing its low-frequency voltage fluctuation are critical challenges that need to be addressed. To address these challenges, this paper proposes a "variable reference + zero-sequence injection" method that requires only three reference voltage signals to determine the injected zero-sequence components. Particularly, the expression of the midpoint current, regarding the modulation index and phase current amplitude, is theoretically derived. This reveals the fundamental connection between the zero-sequence voltage signal and the midpoint current, providing a theoretical foundation for the zero-sequence injection method in four-level inverters. Subsequently, a simulation model and an experimental platform of the 4L-ANPC inverter were developed to compare and analyze the waveforms of the upper and lower capacitor voltages, phase currents, and line voltages under different modulation methods. Additionally, the upper and lower capacitor voltage waveforms were examined for various modulation indices. The results indicate that as the modulation index increases, the low-frequency voltage fluctuation in the upper and lower capacitor voltages also rises. At a modulation index of 0.95, the "variable reference + zero-sequence injection" method effectively suppresses the fluctuation in the upper and lower capacitor voltages to be no more than 1 V. These experimental findings validate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The distributed generation (DG) scheme has become significant and advanced energy generation corridor for present power distribution system. This advanced DG scheme offers several merits such as flexible active power transfer, low transmission losses, maximize power efficiency, reduce transmission cost, expanding grid capacity, so on. It is motivated that, integration of such DG system in to multi-parallel feeder distribution system with enhanced power-quality features is considered as major problem statement. The proposed multi-functional unified power-quality conditioner (MFUPQC) device has robust design, reliable performance; specifically for addressing the voltage-current affecting PQ issues, regulation of activepower in multi-parallel distribution system. The fundamental goal of the MFUPQC device has been to operate as both a PQ improvement device and a DG integration device by implementing a new universal fundamental vector reference (UFVR) control algorithm. The suggested innovative control algorithm extracts the fundamental voltage and current reference signals with low computational response delay, simple mathematical formulations and without additional transformations which are also major problems identified in classical control schemes. This work focuses on design, operation and performance of MFUPQC device has been evaluated in both PQ and DG operations in a multi-parallel feeder distribution system through MATLAB/Simulink computing platform. The simulation results are illustrated with possible interpretation and analysis. [ABSTRACT FROM AUTHOR]

With the continuous advancement of electronic technology, the application of high-voltage integrated circuits is becoming increasingly prevalent in fields such as power systems, medical devices, and industrial automation. The reference circuit within high-voltage integrated circuits must not only exhibit insensitivity to temperature variations but also maintain stability across a broad voltage supply. This paper presents a bandgap reference (BGR) source capable of operating over a wide input range. This BGR employs a high-order curvature compensation method to eliminate nonlinear voltage terms, resulting in minimal temperature drift. The circuit achieves an impressive temperature coefficient (TC) of 0.88 ppm/°C over a temperature range from −40 °C to 130 °C. To ensure stable operation within a 4–40 V range, the design incorporates a pre-regulation circuit that stabilizes the supply voltage of the BGR core at a fixed value, thereby enhancing the ability to withstand variations in power supply voltage. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

ABSTRACT This article describes an energy‐efficient, low‐power CMOS temperature sensor suitable for portable applications. The sensor's front‐end circuitry is designed with a reference voltage (VREF$$ {}_{REF} $$), complementary to absolute temperature (CTAT) voltage (VCTAT$$ {}_{CTAT} $$), and ramp voltage generators. The ramp voltage (Vcap$$ {}_{cap} $$) is produced by utilizing a current reference circuit. The ramp voltage is compared with independent and temperature‐dependent voltages to perform the voltage‐to‐frequency conversion. Conversion from frequency to digital output is achieved through an asynchronous counter with an on‐chip oscillator. The proposed design is realized in a 0.18‐μ$$ \upmu $$m CMOS technology and attains a power usage of 604.4 nW at 27°C with an operating voltage of 0.5 V. Furthermore, it obtains an inaccuracy of +0.71/−0.73°C over −40°C to 125°C temperature range with an active area of 0.025 mm2. Moreover, the designed sensor circuit offers a resolution of 0.17°C with an energy conversion of 96.7 pJ. [ABSTRACT FROM AUTHOR]

This article introduces an affine registration (AR) algorithm to improve the performance of ultra-local (UL) model-free predictive control (MFPC) methods. The UL model is extensively utilized in continuous control set (CCS)-MFPC to estimate lumped parameters. However, in these cases, variations in inductance during operation can significantly impact the input gain coefficient of the UL model. Little work has focused on this aspect, which makes the motivation and novelty of this paper. The AR technique, derived from image processing methodologies, is employed to establish a mapping between predicted states and actual states during the commissioning process. Subsequently, during actual operation, the resolved voltage reference is modified based on the AR matrix to compensate for errors in the UL model. The theoretical control model is rigorously derived, and experimental results are presented to validate the superior performance of the proposed method. [ABSTRACT FROM AUTHOR]

Power management chips is damaged to varying degrees when they work at the ambient temperature beyond their acceptable range, and the over-temperature protection circuit plays an important role in improving the reliability and robustness of this kind of chip. This study designs a high-precision over-temperature protection circuit with the dual functions of turning off when the temperature is too high and reminding when the temperature is too low. The positive and negative temperature coefficient voltages are used to detect the chip temperature in real time, and then four logic turnover points are obtained by comparing them with different reference voltages at the output end of the band-gap reference circuit. After processing by the high-precision comparator circuit and hysteresis logic circuit, the hysteresis logic signals are output to control the working state of the chip or to remind the low temperature. The design and relevant simulation have been carried out based on 0.18 μm BCD(Bipolar-Complementary Metal Oxied Semiconductor-Double diffused Metal Oxide Semiconductor) process, and the simulation results show that when the power supply voltage ranges from 3.0~ 5.5 V, the maximum offset of the temperature threshold corresponding to the hysteresis logic turnover signal at the output end of the circuit is within 0.3℃. The circuit has high precision and can be widely integrated in various power management chips requiring over-temperature protection. [ABSTRACT FROM AUTHOR]

A new energy industry represented by photovoltaic and wind power has been developing rapidly in recent years, and its randomness and volatility will impact the stable operation of the power system. At present, it is proposed to enrich the regulation of the power grid by tapping the regulation potential of load-side resources. This paper evaluates the overall voltage regulation capability of substations under the premise of considering the impact on network voltage security and providing a theoretical basis for the participation of load-side resources of distribution networks in the regulation of the power grid. This paper proposes a Zbus linear power flow model based on Fixed-Point Power Iteration (FFPI) to enhance power flow analysis efficiency and resolve voltage sensitivity expression. Establishing the linear relationship between the voltages of PQ nodes, the voltage of the reference node, and the load power, this paper clarifies the impact of reactive power compensation devices and OLTC (on-load tap changer) tap changes on the voltages of various nodes along the feeder. It provides theoretical support for evaluating the voltage regulation range for substations. The day-ahead focus is on minimizing network losses by pre-optimizing OLTC tap positions, calculating the substation voltage regulation boundaries within the day, and simultaneously optimizing the total reactive power compensation across the entire network. By analyzing the calculated examples, it was found that a pre-scheduled OLTC (on-load tap changer) can effectively reduce network losses in the distribution grid. Compared with traditional methods, the voltage regulation range assessment method proposed in this paper can optimize the adjustment of reactive power compensation devices while ensuring the voltage safety of all nodes in the network. [ABSTRACT FROM AUTHOR]

In electrocardiograms (ECGs), multiple forms of encryption and preservation formats create difficulties for data sharing and retrospective disease analysis. Additionally, photography and storage using mobile devices are convenient, but the images acquired contain different noise interferences. To address this problem, a suite of novel methodologies was proposed for converting paper-recorded ECGs into digital data. Firstly, this study ingeniously removed gridlines by utilizing the Hue Saturation Value (HSV) spatial properties of ECGs. Moreover, this study introduced an innovative adaptive local thresholding method with high robustness for foreground–background separation. Subsequently, an algorithm for the automatic recognition of calibration square waves was proposed to ensure consistency in amplitude, rather than solely in shape, for digital signals. The original signal reconstruction algorithm was validated with the MIT–BIH and PTB databases by comparing the difference between the reconstructed and the original signals. Moreover, the mean of the Pearson correlation coefficient was 0.97 and 0.98, respectively, while the mean absolute errors were 0.324 and 0.241, respectively. The method proposed in this study converts paper-recorded ECGs into a digital format, enabling direct analysis using software. Automated techniques for acquiring and restoring ECG reference voltages enhance the reconstruction accuracy. This innovative approach facilitates data storage, medical communication, and remote ECG analysis, and minimizes errors in remote diagnosis. [ABSTRACT FROM AUTHOR]

Severe torque ripple and determination of the weighting factor pose significant challenges in traditional predictive torque control. A deadbeat predictive torque control scheme designed to minimize torque ripple for dual three-phase permanent magnet synchronous motors is proposed in this paper, eliminating the need for a cost function. Additionally, a novel method for calculating action time based on geometric principles is proposed. First, the deadbeat direct torque and flux control is employed to obtain the reference voltage vector. To reduce the computational burden, the nearest virtual voltage vector is selected directly without a cost function. Subsequently, the torque ripple is further reduced by calculating the corresponding action time based on the introduced geometric relationship in the volt-sec coordinate system. Finally, experimental results demonstrate the effectiveness of the torque ripple reduction method under different working conditions. [ABSTRACT FROM AUTHOR]

This work presents a sub-nanowatt voltage reference (VR) achieving a high-power supply ripple rejection (PSRR). It utilizes a self-current biasing circuit to reduce the voltage dependency of the output voltage (VREF) to the power supply variations. For low-power operation, all transistors operate in the subthreshold region. The design's performance is verified through post-layout and Monte Carlo simulations in a standard 180 nm CMOS process. Results show that the proposed bandgap achieves an output voltage of 0.150 V with a PSRR of -81.5 dB at Vdd = 1V. Notably, it eliminates the need for an additional startup circuit and consumes only 0.72 nW at T = 27°C with Vdd = 0.5V. The proposed voltage reference exhibits a temperature coefficient (TC) of approximately 18 ppm/°C over a temperature range of -20°C to 130°C while without using a trimming circuit a reasonable (σVREF/μVREF) = 2.3% is obtained. This design's average line sensitivity (LS) is 0.072%/V (Vdd = 0.5V to 1.8V). However, the PSRR and LS values are temperature-dependent. At the high temperature of 130°C (worst-case), the PSRR and LS degrade to approximately -80.45 dB and 0.084 %/V, respectively. The output noise at the frequency of 1 KHz is obtained as 167.34 nV/√ Hz. The proposed VR occupies a small active area of 513.5 μm2. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive control (MPC) strategy to regulate output voltages in a multi-modular matrix converter topology for isolated loads. The converter system harnesses power from a six-phase permanent magnet synchronous generator (PMSG) to deliver sinusoidal voltages to a three-phase load, with LC filters positioned at the output of each MC module within the multi-modular scheme. The proposed MPC approach ensures that the output voltages remain within acceptable ranges of magnitude, phase, and frequency, even under load variations and system faults. This control strategy is particularly suitable for uninterruptible power supply systems, microgrids or other applications where voltage regulation is critical. Experimental studies validate the effectiveness of the control strategy under various load conditions, reference voltage changes, and simulated system fault scenarios. The results highlight the robustness and reliability of the proposed voltage control using the multi-modular matrix converter. [ABSTRACT FROM AUTHOR]

A picowatt CMOS voltage reference with dual outputs is proposed and simulated in this paper based on a standard 65 nm process. To compensate for the leakage current caused by parasitic reverse-biased PN junctions, an approach employing gate leakage transistors is proposed. Maintaining a maximal temperature coefficient (TC) of 20.40 ppm/°C across an extended temperature range of −10∼155 °C is achieved. Additionally, a voltage divider consisting of diode-connected NMOS transistors is introduced to obtain a lower voltage output without shunting the original branch or utilizing operational amplifiers. Moreover, a novel trimming block is utilized to optimize TC across different process corners. Simulation results demonstrate that a minimum power consumption of only 53.83 pW is achieved and the line sensitivity is 0.077%/V with 0.45 V to 2.5 V supply. The power supply rejection ratio of −76.70 dB at 10 Hz and V D D = 1.8 V is obtained. [ABSTRACT FROM AUTHOR]

The need for low power consumption in highly integrated systems-on-chip (SoCs), such as IoT-based smoke detection systems, has made frequent power-ups and power-downs a common practice. Although the device performance degradation caused by such frequent power-ups and power-downs is ignored in most circuit studies, in high-precision bandgap voltage references, the degradation of particular devices can result in a reference voltage shift. This work investigates the effects of frequent power-ups and power-downs on a simple bandgap reference circuit and demonstrates that the effects are real and non-negligible. Aging simulations based on simple bandgap reference circuits are performed to analyze the causes of device performance degradation and circuit output voltage shifts. The simulation results show that frequent power-ups and power-downs induce the negative bias temperature instability (NBTI) effect, a phenomenon that causes performance degradation in devices, such as threshold voltage degradation, under negative bias and high temperature conditions. Further, gate voltage waveforms of these devices were extracted for aging tests and the results of the tests in 14 nm FinFET and the NBTI aging model were used to infer the threshold voltage shift after 10 years at 125 °C. A circuit modification is proposed to mitigate the degradation of device performance and reference voltage shift. This work indicates that NBTI stresses introduced by frequent power-ups and power-downs need to be considered in circuit design. [ABSTRACT FROM AUTHOR]

In order to solve the issues of large computation and control performance affected by motor parameters in the conventional model predictive torque control (MPTC) of permanent magnet synchronous motors (PMSMs), a robust model predictive torque control strategy with online parameter identification based on an improved differential evolution extended Kalman filter (IDEEKF-RMPTC) is proposed To begin with, and a steady-state voltage vector at the next time is obtained through a low-pass filter and used as the reference voltage vector to select the alternative voltage vector. The parameter robustness of the PMSM system is enhanced, and the computational effort is reduced. In addition, an improved differential evacuation algorithm for the extended Kalman filter (EKF) is designed, and the system noise matrix Q and measurement noise matrix R of the EKF are optimized. The estimation error is reduced; the stability of the system is enhanced; and the accuracy of the identification of the motor parameters is improved. Finally, the computational effort of the system is effectively reduced by the proposed IDEEKF-RMPTC strategy, and the parameter robustness of the PMSM drive system under parameter mismatch conditions is enhanced which are proved by the experimental results. [ABSTRACT FROM AUTHOR]

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell's quiescent current to a multiple of a reference current and each cell's static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA. [ABSTRACT FROM AUTHOR]

This paper presents a sub-1-V CMOS bandgap reference circuit with ultra-low power consumption, utilizing only 9 MOS transistors. The proposed circuit achieves nano-watt power consumption by biasing all transistors in the sub-threshold region. A three-branched configuration is utilized to create the bandgap voltage reference in the circuit. The proposed architecture generates CTAT and PTAT voltages without using any op-amp and BJT. In this circuit, the cascode structure are used to improve the line sensitivity (LS). In the proposed bandgap circuit, self-biased configuration is used without using an external bias circuitry. The first branch generates PTAT current and the second and third branches generate PTAT and CTAT voltages. The bandgap circuit is designed and simulated using Cadence in TSMC 0.18 μm CMOS technology. The results of post-layout simulation indicate that the bandgap voltage reference circuit generates a voltage reference of 644 mV, with a temperature coefficient (TC) of 78.5 ppm/°C within the temperature range of − 25 to 85 °C. The proposed circuit operates with a power supply of 0.9 V and consumes only 8.2 nW. Furthermore, the circuit exhibits a line sensitivity of 0.31%/V for power supply voltages ranging from 0.9 to 1.8 V. The Power Supply Ripple Rejection (PSRR) of the proposed circuit is about − 40 dB within the frequency range of 1–100 Hz. [ABSTRACT FROM AUTHOR]

This study presents the design and implementation of an efficient off-grid photovoltaic (PV)-powered motor-pump system utilizing a two-stage power converter. The system integrates a neural network-based maximum power point tracking (MPPT-NN) algorithm with a proportional integral (PI) controller and an additional bidirectional PI charger. Controller gains are optimized using ant colony optimization (ACO) to achieve optimal performance. The proposed MPPT-NN-PI/ACO controller enhances control responses and improves energy utilization efficiency by 17% compared to traditional PI controller. Performance comparisons of MPPT techniques demonstrates that the proposed controller outperforms several existing methods, including commercial on-off controllers, the modified Perturb & Observe algorithm, and neural network-based controllers, by approximately 4%-20%. It shows a slightly different performance of about 1%-6% compared to advanced adaptive controllers, including fuzzy logic and neuro-fuzzy controllers. For bidirectional charger performance, the DC bus voltage connecting the boost converter and bidirectional converter remains stable with small ripples and is well-aligned with the reference voltage, ensuring uninterrupted operation under varying weather conditions. The bidirectional charge management effectively maintains battery state-of-charge (SOC), showing a decline during periods of insufficient PV energy and achieving full charging during periods of excess PV energy. System performance is validated through both simulation and laboratory-scale prototyping, ensuring robust operation. [ABSTRACT FROM AUTHOR]

Lithium-ion (Li-ion) battery has played a key role for the development of electric vehicle (EV) at present, while the Li-ion batteries in the market come from different manufactures. Verifying the performance of the battery management system (BMS) for various battery chemistries is a complex undertaking. This paper proposes a high-fidelity Li-ion battery emulator for EV applications. The emulator utilizes a battery model parameterized by a series of performance tests and a special-designed hardware platform. A three-order battery equivalent circuit model (ECM) is selected to provide the voltage and current reference signal in the processor. Subsequently, the hardware generates the high voltage and current signal in accordance with the reference. To ensure the high accuracy of the battery ECM, a 37 Ah nickel manganese cobalt (NMC) battery was selected for testing under both charge and discharge conditions, as well as across a temperature range of − 30℃ to 45℃. The battery emulator is verified on charge and discharge mode for both accuracy and dynamic performance validations. [ABSTRACT FROM AUTHOR]

Grid-forming inverters (GFMIs) have been identified as critical assets in ensuring modern power system reliability. Their ability to synthesize an internal voltage reference while emulating synthetic inertia has sparked extensive research. These characteristics have recently piqued interest in their capacity to provide blackstart ancillary services. The blackstart of a bulk power system poses significant challenges, namely the large transients from the energization of unloaded transformers, rotational motor loads, and long transmission cables, which have been effectively studied using conventional synchronous generators (SGs). The concept of an inverter-based resource (IBR)-based blackstart continues to be an open research area necessitating further investigations due to the known limitations of IBRs such as low short-circuit current capabilities. This paper presents a blackstart case study of a bulk power system investigating the performances of a conventional SG to a GFMI when utilizing hard switching methods. The paper qualitatively investigates the transient inrush currents from the transformer and rotational load energization sequences. Additional examinations into the significance of the GFMI's current-limiting schemes and voltage control loop compensator gains are presented. Furthermore, the harmonic distortions from the transformer energization sequence are also evaluated. Finally, a full network energization case is presented to demonstrate how both sources can provide blackstart provisioning services. The models are developed in EMTDC/PSCAD using real-world transmission planning data. [ABSTRACT FROM AUTHOR]

316 L steel-based human implants play an important role in the biomedical field. In order to address the problem of immune rejection of 316 L steel-based human implants and further improve the machining efficiency, the surface roughness (SR) and hydrophilicity of 316 L workpieces are improved by electrical discharge machining milling (EDM-milling) instead of die-sinking electrical discharge machining (EDM) and by the incorporation of nano hydroxyapatite (NHAP) powder into the dielectric. The effects of powder concentration of NHAP, reference voltage, peak current, pulse width, and pulse interval on the material removal rate (MRR), electrode wear rate (EWR), SR, and contact angle (CA) of 316 L workpiece processed by powder mixed EDM-milling with NHAP (NHAP-PMEDM-milling) are investigated by single-factor experiment, and comparisons are done with the powder mixed die-sinking electrical discharge machining with NHAP (NHAP-PMEDM). According to the results, the MRR, EWR, SR, and CA of 316 L by NHAP-PMEDM-milling are varied regularly with the variation of experiment parameters. The addition of NHAP powder into deionized water (DW) can reduce the CA of the surface of 316 L steel workpiece to a great extent, with a maximum reduction of 27.9%, while affecting MRR, EWR, and SR very little. In addition, NHAP-PMEDM-milling can increase MRR by 115.5% and reduce EWR, SR, and CA by 43.2%, 13.2%, and 15.9%, respectively, compared with NHAP-PMEDM. [ABSTRACT FROM AUTHOR]

With the rapid development of electronic power systems, DC-DC converters are widely used, including the Four-Switch Buck–Boost (FSBB) converter, which has a unique advantage in scenarios with a wide range of voltage inputs. To improve the response speed and anti-interference capability of the FSBB converter, this paper proposes an adaptive global fast integral terminal sliding mode control method. Through an in-depth analysis of the fundamental characteristics of the FSBB converter, this study employed a global fast integral terminal sliding mode controller combined with an adaptive algorithm to significantly improve the dynamic performance and robustness of the FSBB converter. The simulation and experimental results show that the proposed method could track the reference voltage quickly and accurately in different modes, exhibiting excellent system robustness compared to conventional sliding mode control, terminal sliding mode control, and PID control methods. [ABSTRACT FROM AUTHOR]

Amongst the various topologies of multi-input multi-output (MIMO) DC-DC converters, single-inductor MIMO (SI-MIMO) converters have the advantages of a reduced component count, a simpler structure, and low cost. These converters are suitable in electric vehicle (EV) applications involving variable ports, essential for performing different functions. Digital control in SI-MIMO converters is promising for enhancing transient performance due to its numerous benefits. However, delays in digital control, particularly computational and pulse width modulation (PWM) delays, can negatively impact the performance of DC-DC converters. Multi-sampling and double PWM update methods can mitigate these control delays, but they often necessitate complex control schemes, adding computational burden. In this work, an advanced multi-sampling PWM technique, integrating sample shift and multi-sampling, is proposed while employing a simple digital PID control scheme. The proposed method was tested for a shared-switch SI-MIMO converter with battery discharging and charging modes in the MATLAB/Simulink environment and compared with the conventional single- and multi-sampling PWM methods. The results demonstrated that the proposed method significantly improved the converter performance, surpassing the conventional single- and multi-sampling PWM methods. In the battery discharging mode, utilizing the proposed method, the output voltage achieved a settling time of 0.075 s in response to a step change in its reference, significantly outperforming multi-sampling, which yielded a settling time of 0.124 s, and single sampling, which exhibited an even longer settling time of 0.898 s. It also demonstrated a minimal overshoot of 0.06 volts compared to 1.5 volts with multi-sampling during the step change in the input voltage. Similarly, in the battery charging mode, upon a step change in the reference output voltage, the proposed method effectively minimized the overshoot of the output voltage to 0.845 volts compared to 1.175 volts with multi-sampling, and it decreased the inductor current settling time to 0.296 s from 0.330 s recorded under multi-sampling. These findings underscore the potential of the proposed method in enhancing the digital control performance of SI-MIMO DC-DC converters in electric vehicles. [ABSTRACT FROM AUTHOR]

The proposed modified higher gain boost converter employs switched Inductor and multiplier cell-based voltage boosting techniques, as the paper represents. This converter is modelled to enhance the static gain and efficiency. As the designed topology has an incessant source current at its input side, it is ideal for solar PV applications. With a power capacity of 100 W, the proposed topology is designed to work on 24 V source input and 200 V load/output voltage. The load voltage is maintained by a PI controller, which achieves the highest efficiency of 92% under rated load conditions. The converter’s transient performance with the controller is investigated under various situations, including supply voltage variation, reference voltage variation, and load power variation. Finally, the designed converter’s experimental model is created to evaluate the simulated and conceptual results. [ABSTRACT FROM AUTHOR]

Copyright of Electric Machines & Control / Dianji Yu Kongzhi Xuebao is the property of Electric Machines & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper investigates the stability and reliability analysis of a non‐isolated high‐gain DC‐DC converter. The proposed DC‐DC converter produces a high gain output voltage with a lower duty ratio and reduced voltage stress on the semiconductor switch. A reliability analysis is performed to predict the failure rate and lifetime of the individual components using the military handbook (MIL‐HDBK‐217F). A state space equation and small signal modeling of the proposed converter are derived to elucidate the performance of the proposed converter through stability analysis. A closed‐loop using PID controller is incorporated to attain the constant regulated output voltage during sudden parameter changes. The validation of the closed‐loop using the PID controller is verified with the wide range of variations in the different parameters, such as input voltage, load value, and reference voltage value. The laboratory‐based prototype is developed for the proposed converter and validated the performance with 250 W. The power density and efficiency of the proposed converter are 1.360 kW/L and 93%, respectively. [ABSTRACT FROM AUTHOR]

In recent times, photovoltaic (PV) power generation has been growing due to increase in energy demand. In grid-connected mode, achieving maximum power (MP) from the PV array is difficult by using conventional techniques due to various reasons like low tracking efficiency, stability issues, etc. This motivates the design of an appropriate control strategy to obtain the maximum power point tracking (MPPT) to harvest MP from the PV array. This paper proposes a combined higher order sliding mode observer (HOSMO)–super-twisting control (STC) for a grid-connected scenario. A perturb and observe (P &O) technique is employed to generate reference voltage, and a HOSMO is proposed to drive the STC by estimating the inductor current of the PV boost converter. The proposed controller performance is evaluated based on response time across various scenarios, including generation changes, dynamic faults, islanding and resynchronization, and load variations in comparison to other existing controllers. These microgrid test cases have been thoroughly simulated, and their effectiveness has been validated in real-time using OPAL-RT (OP4510). [ABSTRACT FROM AUTHOR]

Fuel cell electric vehicles (FCEVs) are estimated as the future's mobile distributed generators with vehicle-to-grid (V2G) functions. Besides, V2G topologies are required to be designed with an appropriate analog filter by accurately measuring the reference current and voltage values of inverters and converters. Thus, the highest accuracy is required in control structures for charging and grid connection of FCEVs to improve the power quality (PQ). In this study, PQ improvement of V2G operation of FCEVs is proposed by considering the developed real-time digital infinite impulse response (IIR) filters in generating reference signals in the power calculation stage. A band-pass digital IIR filter design is realized with the inverter using LabVIEW infrastructure, and reference signals are smoothed by using IIR filters. The performances of developed different IIR filters' results are examined in the study. Developed filters are designed using the order estimation method. Elliptic, Chebyshev, and Butterworth filters are applied to the voltage and current signals, and the best results are obtained in reference power signals with the Butterworth filter. The Butterworth filter maintains stability in current RMS, induces a 0.09 % decrease in voltage RMS, and shows a slight 0.30 % increase in active power. The proposed approach removes distortions in reference power signals by using a designed filter for a reliable V2G operation of FCEVs. [Display omitted] • IIR filters are proposed to generate reference signals for FCV2G operation. • Butterworth filter demonstrated superior stability in current and voltage RMS. • IIR filters are designed using the improved order estimation method in LabVIEW. • Improving calculation process increases PQ in grid connection of FCEVs with V2G. • A real-time test system in laboratory is presented verifying proposed approach. [ABSTRACT FROM AUTHOR]

This paper introduces an MOS-based intelligent temperature sensor with a linear readout. Compared with similar designs, the proposed sensor utilizes the DIBL effect to reduce the precision requirement for the voltage reference source and compensate for the temperature measurement range. A compact voltage reference circuit is introduced, which generates two reference voltage bases using only three transistors. In addition, the proposed digital readout circuit does not require a subtractor or a divider, further saving area. Fabricated in a 55 nm CMOS process, the proposed sensor occupies a compact area of 3216 μ m 2 . Post-simulation results show it has a maximum error of −0.52/+0.28 °C within the temperature range of −20 °C to 120 °C after two-point calibration. The power supply voltage range of the sensor is 0.8 to 1.8 V. It has a maximum voltage sensitivity of 5.7 °C/V and its power consumption is only 166 nW, with a power supply voltage of 0.8 V. [ABSTRACT FROM AUTHOR]

At the present time, phase auto-adjustment systems are widely used, in which frequency stabilization and frequency tracking is achieved due to phasing of the reference (setting) and control voltages. Frequency autoadjustment systems solve this problem as a result of direct measurement of the difference in frequencies of the reference and control voltages, and reduction of this difference. The scientific task solved in the research is to increase the dynamic characteristics of automatic tuning systems, to increase the dynamic accuracy and speed of frequency auto-tuning systems of radio monitoring devices with astatism. Therefore, the object of research is the system of automatic self-adjustment of military radio monitoring equipment. The subject of the research is the dynamic, root mean square errors of automatic self-tuning systems under different laws of change of the disturbing influence (input signal frequency deviation) and the speed of the systems. The methods of analysis and synthesis, the theory of complex technical systems and the theory of radio receiving devices were chosen as the basic mathematical apparatus in the proposed research. The research proposed a combined system of frequency auto-adjustment of radio monitoring devices with astatism, as well as basic mathematical expressions that describe its operation. In the process of research the following tasks were solved: – an analysis of the dynamic characteristics of a static system of frequency auto-adjustment with the principle of deviation control was performed; – a functional scheme and a mathematical model of a combined frequency auto-adjustment system with firstorder astatism and increased speed were developed. One of the important advantages of the proposed mathematical model is the increased efficiency of frequency tuning depending on the type of signal compared to known frequency autotuning. This is accepted not only in the case of changes in the disturbing influence according to deterministic laws, but also in the case of random disturbing influence. The direction of further research should be considered the increase in dynamic accuracy (reduction of dynamic, root mean square errors) and speed of frequency auto-adjustment systems. [ABSTRACT FROM AUTHOR]

The increasing participation of photovoltaic sources in power grids presents the challenge of enhancing power quality, which is affected by the intrinsic characteristics of these sources, such as variability and lack of inertia. This power quality degradation mainly generates variations in both voltage magnitude and frequency, which are more pronounced in microgrids. In fact, the magnitude problem is particularly present in the distribution systems, where photovoltaic sources are spread along the grid. Due to the power converter's lack of inertia, frequency problems can be seen throughout the network. Grid-forming control strategies in photovoltaic systems have been proposed to address these problems, although most proposed solutions involve either a direct voltage source or energy storage systems, thereby increasing costs. In this paper, a photovoltaic injection system is designed with a virtual synchronous machine control strategy to provide voltage and frequency support to the grid. The maximum power point tracking algorithm is adapted to provide the direct voltage reference and inject active power according to the droop frequency control. The control strategy is validated through simulations and key experimental setup tests. The results demonstrate that it is possible to inject photovoltaic power and provide voltage and frequency support. [ABSTRACT FROM AUTHOR]

To enhance the sensitivity, signal-to-noise ratio and durance of electrospray mass spectrometer, an off-axis ion guide combining a traveling-wave (TW) stacked-ring and a shaped ion funnel has been designed, which is capable of filtering out the neutral contaminants and charged droplets entrained in the electrospray plume. According to its structural characteristics, the corresponding TW and radio frequency (RF) coupling power supply and measurement as well as control system were designed. Customizable Ethernet communication protocol was used to control the field-programmable logic gate array (FPGA) for full-circuit signal control and generation, and an 8-channel traveling-wave amplitude monitoring was achieved through a 12-bit analog-to-digital converter (ADC) and a 16-bit digital-to-analog converter (DAC). In addition, dual-plane transformer coupling circuit was designed. The use of traveling wave changed the central reference frame of the RF, achieving the purpose of programmed RF and the effect of TW in the stacked-ring to provide axial kinetic energy. The stability and accuracy of the electrical parameters of the hardware system on the off-axis transmission structure were tested. The results showed that the controllable voltage range of TW power supply is 0.1-100 V and the controlled DC power supply’s full range detection and control absolute error are less than 0.04 V. The frequency of TW up to 400 kHz, both rising edge and falling edge are less than 30 ns. Furthermore, the waveforms of TW, RF and post-coupling waveform are sufficiently smooth. The test results also showed that the performance of the power supply and measurement and control system are stable and reliable, and their accuracy and range can satisfy the design requirements. Then, the performance of off-axis structure was tested under rough vacuum using reserpine ions. It was found that the reference voltage difference between the upper and lower traveling-waves (the voltage which the ions were extracted), the voltage of the upper traveling-waves, and the traveling-wave duty cycle of the off-axis ion transmitter have more significant effects on the off-axis transmission of ions than other electrical parameters. The experimental results provide a fundamental understanding of ion transport and off-axis separation of traveling-wave stacked-ring structures, which is valuable for the development of high signal-to-noise mass spectrometry system. In the future, this novel traveling-wave off-axis transmitter and its coupling power supply system will be applied to homemade mass spectrometry instruments. Besides, we will compare the developed device with the mainstream ion transmission devices in the market so as to further improve the device structure and power supply parameters, and deeply explore the role of traveling-wave off-axis transmitter in different ionization sources and different detectors. [ABSTRACT FROM AUTHOR]

Summary: Maintaining proper current sharing among distributed generation (DG) units while regulating the output voltage is a challenging control issue in DC microgrids. The conventional droop control is widely used at the primary level of control to tackle this issue, but this method faces some limitations in voltage control and current sharing. To address this problem, this paper presents a new distributed secondary control method that determines the resistance of transmission lines by injecting an external pulse to the reference voltage of each converter and measuring output voltage and current changes. The proposed secondary control signal, denoted as Ui, enables simultaneous proportional current sharing and voltage restoration in the DC microgrid by correcting the droop coefficients based on the determined resistances. In order to ensure the stability of the proposed method, the small signal stability analysis of the closed‐loop system is conducted, considering various parameter changes. In contrast to similar methods, the proposed method introduces a new hybrid technique of voltage setpoint shifting and droop parameter adjustment that achieves precise proportional current sharing and voltage restoration, even when faced with varying resistive loads and constant power loads (CPLs). Additionally, the proposed method demonstrates outstanding characteristics, such as high convergence speed, the ability to determine transmission line resistances instead of assuming them to be known, and robustness in plug‐and‐play scenarios and communication system failures. The simulation results in MATLAB and experimental tests confirm the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Featured Application: The proposed surge arrester is applied to a DC GIS in an offshore wind farm converter platform, significantly reducing the space the equipments take up by up to 95%, which performs well especially in the new power system. The employment of a multi-column parallel connection is intended to enhance the energy absorption capability and reliability of surge arresters. However, the disparity in reference voltage between each varistor column and the uneven current distribution may result in a reduction in performance or even failure of the surge arrester. The objective of this study is to investigate the spiral structure of a ±550 kV DC gas-insulated switchgear (GIS) parallel arrester and its influence on the current distribution characteristics. This research develops a model of a ±550 kV DC GIS arrester and performs an in-depth theoretical analysis using multi-physics field simulations. Subsequently, a ±66 kV miniature prototype is constructed, and the accuracy of the theoretical analysis and simulation results is validated by experiments, validating the effectiveness of the proposed method. This study calculates the self-generated inductance in the spiral structure of ZnO varistors using simulations. The influence of the self-generated inductance on the current distribution of the multi-column arrester when absorbing energy is further investigated. The results indicate that the self-generated inductance of the spiral structure can reduce the current deviation factor by 28–65%. This research provides a novel approach to improving current equalization in the parallel surge arresters of DC GISs for offshore wind power converter platforms. [ABSTRACT FROM AUTHOR]

This paper presents a novel fuzzy-augmented model reference adaptive voltage regulation strategy for the DC–DC buck converters to enhance their resilience against random input variations and load-step transients. The ubiquitous proportional-integral-derivative (PID) controller is employed as the baseline scheme, whose gains are tuned offline via a pre-calibrated linear-quadratic optimization scheme. However, owing to the inefficacy of the fixed-gain PID controller against parametric disturbances, it is retrofitted with a model reference adaptive controller that uses Lyapunov gain adaptation law for the online modification of PID gains. The adaptive controller is also augmented with an auxiliary fuzzy self-regulation system that acts as a superior regulator to dynamically update the adaptation rates of the Lyapunov gain adaptation law as a nonlinear function of the system's classical error and its normalized acceleration. The proposed fuzzy system utilizes the knowledge of the system's relative rate to execute better self-regulation of the adaptation rates, which in turn, flexibly steers the adaptability and response speed of the controller as the error conditions change. The propositions above are validated by performing tailored hardware experiments on a low-power DC–DC buck converter prototype. The experimental results validate the improved reference tracking and disturbance rejection ability of the proposed control law compared to the fixed PID controller. [ABSTRACT FROM AUTHOR]

A fixed-slope soft-start method applicable to Buck converters for on-chip integration is proposed to address the issue of varying power stresses (device voltage, current stress) during start-up with different output voltages. The main mechanism involves combining feedback coefficient sampling with a fixed-slope reference voltage to achieve a slow rise in the reference voltage by equating the soft-start charging current to a pulse current through the on-chip integration of a small capacitor. This allows for fixed-slope start-ups for different set output voltages. Spike elimination techniques are employed to address charging current spikes caused by pulse periods, enhancing precise control over the soft-start time. By replacing the traditional resistor divider network with a capacitive divider network in the soft-start method, DC power consumption is minimized. Upon completion of the soft start, a smooth transition to a steady-state operation occurs, with the automatic shutdown of the soft-start module reducing static power consumption. A specific circuit design and layout verification based on 0.18 μm high-voltage BCD technology demonstrates that the proposed method maintains a fixed-slope start-up of approximately 5 mV/μs within the chip's output range of 0.9 V to 4 V, with a slope control accuracy of up to 98%. The soft-start circuit effectively eliminates surge currents generated during start-up under full load conditions of 3 A and no-load conditions of 0 A, reducing the overall surge current by 44% and enabling a stable voltage rise and the smooth transition to a steady-state operation. [ABSTRACT FROM AUTHOR]