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Keyword extraction is one of the most important aspects of text mining. Keywords help in identifying the document context. Many researchers have contributed their work to keyword extraction. They proposed approaches based on the frequency of occurrence, the position of words or the similarity between two terms. However, these approaches have shown shortcomings. In this paper, we propose a method that tries to overcome some of these shortcomings and present a new algorithm whose efficiency has been evaluated against widely used benchmarks. It is found from the analysis of standard datasets that the position of word in the document plays an important role in the identification of keywords. In this paper, a fuzzy logic-based automatic keyword extraction (FLAKE) method is proposed. FLAKE assigns weights to the keywords by considering the relative position of each word in the entire document as well as in the sentence coupled with the total occurrences of that word in the document. Based on the above data, candidate keywords are selected. Using WordNet, a fuzzy graph is constructed whose nodes represent candidate keywords. At this point, the most important nodes (based on fuzzy graph centrality measures) are identified. Those important nodes are selected as final keywords. The experiments conducted on various datasets show that proposed approach outperforms other keyword extraction methodologies by enhancing precision and recall. [ABSTRACT FROM AUTHOR]

Wireless sensor network (WSN) is a group of interconnected sensor nodes that work wirelessly to capture the information of surroundings. The routing of the network is a challenging task. The routing of WSN is classified as proactive, reactive, and hybrid. Adhoc on-demand distance vector (AODV) routing is an example of reactive routing based on the demand route formations among different nodes in the network. The research article emphasizes the design and simulation of the AODV routing hardware chip using very-high-speed integrated circuit hardware description language (VHDL) programming in Xilinx integrated synthesis environment (ISE) 14.7 software. The performance of the chip is studied based on the field-programmable gate array (FPGA) hardware parameters such as slices, lookup table (LUTs), input/output block (IOB), flipflops, and memory for the different configurations of the network (N = 10, 20 ....100). The delay and frequency are also estimated on the Virtex-5 FPGA. The performance of the WSN with AODV routing is also analyzed based on the packet delivery ratio, throughput, delay, and control overhead. The simulation test cases verified the 8-bit, 64-bit, and 128-bit data communication within the nodes. [ABSTRACT FROM AUTHOR]