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Modular multilevel converter (MMC) is considered as a good technology for high-voltage direct current (HVDC) transmission systems. It can generate a good quality staircase output voltage waveform due to the cascaded connection of large number of identical sub-modules (SMs). Energy variations in SM capacitor lead to capacitor voltage fluctuations which affect the size and stability of MMC. Traditionally MMC arm voltages are controlled using direct modulation method. The closed loop and open loop compensated modulation methods are implemented to overcome the drawbacks created in direct modulation method. However, these methods rely on the accurate measurements or estimation of SM capacitor voltages. In this paper, capacitor energy variations in MMC based on direct modulation method under three different categories using proportional-resonant (PR) controllers are discussed as (a) pure sinusoidal arm current (b) sinusoidal arm current with addition of large 2nd harmonic (c) sinusoidal arm current with addition of 2nd +4th harmonics. Analytical and simulation results show reduction in capacitor energy variations in MMC while injecting harmonics in the arm currents using direct modulation method.

Modular multilevel converter (MMC) is a type of voltage source converter (VSC) that offers several advantages, permitting suitable technology in high voltage direct current (HVDC) transmission systems. In the conventional non-energy-based control method, current does not manage capacitor energies inside MMC modules and produces DC current oscillations. Whereas in energy-based control methods, oscillations in DC current are reduced as differential currents are controlled. In this paper a proportional resonant (PR) controller is designed to reduce oscillations in a DC-link of an HVDC system using non-energy-based control method. It reduces oscillations by injecting even order harmonics in MMC. The proposed method is tested on a symmetrical monopole point-to-point MMC-HVDC system using PSCAD simulation software. Furthermore, the proposed method is also compared with a conventional repetitive current (RC) controller using bode plots. Analytical and simulation results validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper studies the losses in the magnets of a permanent-magnet synchronous machine (PMSM) with surface magnets caused by square voltage pulse width modulation (PWM) waveforms. First, the conductivity of the magnets is determined. Second, the effect of segmentation on the losses is calculated by a 3-D time-harmonic finite element model for sinusoidal waveforms. More segmentation of the magnets in axial and circumferential direction results in much lower losses in the magnets, but more losses in the massive rotor yoke. In a third step, the losses are simulated and measured on an experimental PMSM for square waveforms generated by PWM. Superposition of appropriate sinusoidal losses obtained by a time-harmonic FEM seems to be acceptable in order to predict losses in a PMSM for square voltage waveforms. Index Terms--Finite element analysis, inverse problems, losses, permanent magnet machines.

When power-factor correction (PFC) converters designed for operation in continuous-conduction mode (CCM) at full power are operated at reduced load, operation in discontinuous-conduction mode (DCM) occurs in a zone that is close to the crossover of the line voltage. This zone will gradually expand with decreasing load to finally encompass the entire line cycle. Whereas, in CCM, the parasitic capacitances of the switches only cause switching losses, in DCM, they are a source of converter instability, resulting in significant input-current distortion. In this paper, this source of input-current distortion is analyzed, and a solution is proposed. Experimental results are obtained using a digitally controlled boost PFC converter, which is designed to operate in CCM for 1 kW. Index Terms--Discontinuous-conduction mode (DCM), power-factor correction (PFC), snubbers, switch capacitance.

As the performance of microcontrollers has increased rapidly during the last decade, there is a growing interest to replace the analog controllers in low power switching converters by more complicated and flexible digital control algorithms. Compared to high power converters, the control loop bandwidths for converters in the lower power range are generally much higher. Because of this, the dynamic properties of the uniformly-sampled pulse-width modulators (PWMs) used in low power applications become an important restriction to the maximum achievable bandwidth of the control loop. Though frequency- and Laplace-domain models for uniformly-sampled PWMs are very valuable as they improve the general perception of the dynamic behavior of these modulators, the direct discrete design of the digital compensator requires a z-domain model for the combination modulator and converter. For this purpose a new exact small-signal z-domain model is derived. In accordance with the zero-order-hold equivalent commonly used for 'regular' digital control systems, this z-domain model gives rise to the development of a uniformly-sampled PWM equivalent of the converter. This z-domain model is characterized by its capability to quantify the different dynamics of the converter for different modulators, its ease of use and its ability to predict the values of the control variables at the true sampling instants of the real system. Index Terms--Converter modeling, digital control, digital pulse-width modulator (PWM), z-domain model.

Whereas power-factor-correction (PFC) converters for low-power ranges (less than 250 W) are commonly designed for operation in the discontinuous conduction mode, converters for higher power levels are operated in the continuous conduction mode. Nevertheless, when these converters are operated at reduced power, discontinuous conduction mode will appear during parts of the line period, yielding input current distortion. This distortion can be eliminated by employing a dedicated control algorithm, consisting of sample correction and duty-ratio feedforward. The reduction of the harmonic distortion of the input current and the increase of the power factor are demonstrated by experiments on a 1-kW boost PFC converter. Index Terms--Digital control, discontinuous conduction mode (DCM), power-factor correction (PFC).

When a 'classical' current control scheme is applied, the line current of a boost power-factor-correction (PFC) converter leads the line voltage, resulting in a nonunity fundamental displacement power factor and in important zero-crossing distortion in applications with a high line frequency (e.g., 400-Hz power systems on commercial aircraft). To resolve this problem, a current-control scheme is proposed using duty-ratio feedforward. In this paper, the input impedance of the boost PFC converter for both the classical current-loop controller and the controller using duty-ratio feedforward are derived theoretically. A comparison reveals the advantages of the proposed control scheme: a low total harmonic distortion of the line current, a resistive input impedance, virtually no zero-crossing distortion, and a fundamental displacement power factor close to unity. The theoretical results obtained are verified using an experimental setup of a digitally controlled boost PFC converter. Index Terms--Digital control, feedforward systems, input impedance, power-factor correction (PFC), total harmonic distortion (THD), zero-crossing distortion.

Digital control of a boost power factor correction (PFC) converter requires sampling of the input current. As the input current contains a considerable amount of switching ripple and high frequency switching noise, the choice of the sampling instant is very important. To avoid aliasing without employing a (very) high sampling frequency, the sampling is synchronized with the pulse width modulation (PWM). Sampling algorithms employing this technique successfully reject the input current ripple but are not immune to the high frequency switching noise present on all sampled signals. Therefore, a new sampling algorithm, called alternating-edge-sampling and intended for center-based or symmetric PWM, is deduced with as most important features: switching noise immunity, straightforwardness, accurate measurement of the averaged input current and the need for only few processor cycles. The operating principle, design issues and a theoretical study of the input current error induced by the sampling algorithm due to sampling instant timing errors are derived. All theoretical results are validated experimentally for a digitally controlled boost PFC converter switching at 50 kHz. Index Terms--Power factor correction, pulse width modulation, sampling methods.

Resonant techniques like zero-voltage switching (ZVS) and zero-current switching (ZCS) are widely applied to raise the switching frequency and efficiency of converters. An important subclass of converters using resonant techniques is formed by ZVS half- and full-bridge converters. While different varieties of this subclass of converters have been reported, the gate-drive circuit is seldom described. In this paper, a new gate-drive circuit applicable in ZVS half- and full-bridge converters is proposed. The circuit shows excellent features such as transformer isolation, no ringing of the gate--source voltage of the switches, programmable dead time, no active components besides one low-side driver, insensitivity to component value variation, negative gate-source voltage at switch-off, and low drive power. Moreover, the circuit can be used in variable-frequency applications. The theoretical results obtained are verified by experiments. Index Terms--Full-bridge converter, gate-drive circuit, half-bridge converter, zero-voltage switching.