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In the early stages of a novel technology development, it is difficult to provide a comprehensive assessment of its potential capabilities and impact. Nevertheless, some preliminary estimates can be drawn and are certainly of great interest and in this paper we follow this line of reasoning within the framework of the Spin Wave (SW) computing paradigm. In particular, we are interested in assessing the technological development horizon that needs to be reached in order to unleash the full SW paradigm potential such that SW circuits can outperform CMOS counterparts in terms of energy consumption. In view of the zero power SWs propagation through ferromagnetic waveguides, the overall SW circuit power consumption is determined by the one associated to SWs generation and sensing by means of transducers. While current antenna based transducers are clearly power hungry recent developments indicate that magneto-electric (ME) cells have a great potential for ultra-low power SW generation and sensing. Given that MEs have been only proposed at the conceptual level and no actual experimental demonstration has been reported we cannot evaluate the impact of their utilization on the SW circuit energy consumption. However, we can perform a reverse engineering alike analysis to determine ME delay and power consumption upper bounds that can place SW circuits in the leading position. To this end, we utilize a 32-bit Brent-Kung Adder (BKA) as discussion vehicle and compute the maximum ME delay and power consumption that could potentially enable a SW implementation able to outperform its 7nm CMOS counterpart. We evaluate different BKA SW implementations that rely on conversion or normalization gate cascading and consider continuous or pulsed SW generation scenarios. 31nW is the maximum transducer power consumption for which a 32-bit BKA SW implementation can outperform its 7nm CMOS counterpart., Comment: This work has received funding from the European Union's Horizon 2020 research and innovation program within the FET-OPEN project CHIRON under grant agreement No. 801055

We derive an analytical model for the power transfer in a magnetoelectric film bulk acoustic resonator consisting of a piezoelectric--magnetostrictive bilayer. The model describes the dynamic magnetostrictive influence on the elastodynamics via an effective frequency-dependent stiffness constant. This allows for the calculation of both the magnetic and elastic power absorption in the resonator as well as of its energy efficiency when such a resonator is considered as a magnetic transducer. The model is then applied to example systems consisting of piezoelectric ScAlN and magnetostrictive CoFeB, Ni, or Terfenol-D layers., Comment: 39 pages, 9 figures. This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" - CHIRON

We derive a lumped circuit model for inductive antenna spin-wave transducers in the vicinity of a ferromagnetic medium. The model considers the antenna's Ohmic resistance, its inductance, as well as the additional inductance due to the excitation of ferromagnetic resonance or spin waves in the ferromagnetic medium. As an example, the additional inductance is discussed for a wire antenna on top of a ferromagnetic waveguide, a structure that is characteristic for many magnonic devices and experiments. The model is used to assess the scaling properties and the energy efficiency of inductive antennas. Issues related to scaling antenna transducers to the nanoscale and possible solutions are also addressed., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

In this paper, we propose an energy efficient SW based approximate 4:2 compressor comprising a 3-input and a 5-input Majority gate. We validate our proposal by means of micromagnetic simulations, and assess and compare its performance with one of the state-of-the-art SW, 45nm CMOS, and Spin-CMOS counterparts. The evaluation results indicate that the proposed compressor consumes 31.5\% less energy in comparison with its accurate SW design version. Furthermore, it has the same energy consumption and error rate as the approximate compressor with Directional Coupler (DC), but it exhibits 3x lower delay. In addition, it consumes 14% less energy, while having 17% lower average error rate than the approximate 45nm CMOS counterpart. When compared with the other emerging technologies, the proposed compressor outperforms approximate Spin-CMOS based compressor by 3 orders of magnitude in term of energy consumption while providing the same error rate. Finally, the proposed compressor requires the smallest chip real-estate measured in terms of devices., Comment: This work has received funding from the European Union's Horizon 2020 research and innovation program within the FET-OPEN project CHIRON under grant agreement No. 801055. It has also been partially supported by imec's industrial affiliate program on beyond-CMOS logic. F.V. acknowledges financial support from Flanders Research Foundation (FWO) through grant No.~1S05719N

By their very nature, Spin Waves (SWs) consume ultra-low amounts of energy, which makes them suitable for ultra-low energy consumption applications. In addition, a compressor can be utilized to further reduce the energy consumption and enhance the speed of a multiplier. Therefore, we propose a novel energy efficient SW based 4-2 compressor consisting of 4 XOR gates and 2 Majority gates. The proposed compressor is validated by means of micromagnetic simulations and compared with the state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Domain Wall Motion (DWM), and Spin-CMOS technologies. The performance evaluation shows that the proposed compressor consumes 2.5x less and 1.25x less energy than the 22nm CMOS and the conventional SW compressor, respectively, whereas it consumes at least 3 orders of magnitude less energy than the MTJ, DWM, and Spin-CMOS designs. Furthermore, the compressor achieves the smallest chip real-estate. In summary, the performance evaluation of our proposed compressor shows that the SW technology has the potential to progress the state-of-the-art circuit design in terms of energy consumption and scalability., Comment: This work has received funding from the European Union's Horizon 2020 research and innovation program within the FET-OPEN project CHIRON under grant agreement No. 801055

Due to their very nature, Spin Waves (SWs) created in the same waveguide, but with different frequencies, can coexist while selectively interacting with their own species only. The absence of inter-frequency interferences isolates input data sets encoded in SWs with different frequencies and creates the premises for simultaneous data parallel SW based processing without hardware replication or delay overhead. In this paper we leverage this SW property by introducing a novel computation paradigm, which allows for the parallel processing of n-bit input data vectors on the same basic SW based logic gate. Subsequently, to demonstrate the proposed concept, we present 8-bit parallel 3-input Majority gate implementation and validate it by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. To evaluate the potential benefit of our proposal we compare the 8-bit data parallel gate with equivalent scalar SW gate based implementation. Our evaluation indicates that 8-bit data 3-input Majority gate implementation requires 4.16x less area than the scalar SW gate based equivalent counterpart while preserving the same delay and energy consumption figures., Comment: This work has received funding from the European Union's Horizon 2020 research and innovation program within the FET-OPEN project CHIRON under grant agreement No. 801055

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing AND, OR, NAND, NOR and XOR and XNOR functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation., Comment: This work has received funding from the European Union's Horizon 2020 research and innovation program within the FET-OPEN project CHIRON under grant agreement No. 801055

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the $3$-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts., Comment: This work has received funding from the European Union's Horizon 2020 research and innovation program within the FET-OPEN project CHIRON under the grant agreement No. 801055

Spin Waves(SWs) enable the realization of energy efficient circuits as they propagate and interfere within waveguides without consuming noticeable energy. However, SW computing can be even more energy efficient by taking advantage of the approximate computing paradigm as many applications are error-tolerant like multimedia and social media. In this paper we propose an ultra-low energy novel Approximate Full Adder(AFA) and a 2-bit inputs Multiplier(AMUL). We validate the correct functionality of our proposal by means of micromagnetic simulations and evaluate the approximate FA figure of merit against state-of-the-art accurate SW, 7nmCMOS, Spin Hall Effect(SHE), Domain Wall Motion(DWM), accurate and approximate 45nmCMOS, Magnetic Tunnel Junction(MTJ), and Spin-CMOS FA implementations. Our results indicate that AFA consumes 43% and 33% less energy than state-of-the-art accurate SW and 7nmCMOS FA, respectively, and saves 69% and 44% when compared with accurate and approximate 45nm CMOS, respectively, and provides a 2 orders of magnitude energy reduction when compared with accurate SHE, accurate and approximate DWM, MTJ, and Spin-CMOS, counterparts. In addition, it achieves the same error rate as approximate 45nmCMOS and Spin-CMOS FA whereas it exhibits 50% less error rate than the approximate DWM FA. Furthermore, it outperforms its contenders in terms of area by saving at least 29% chip real-estate. AMUL is evaluated and compared with state-of-the-art accurate SW and 16nm CMOS accurate and approximate state-of-the-art designs. The evaluation results indicate that it saves at least 2x and 5x energy in comparison with the state-of-the-art SW designs and 16nm CMOS accurate and approximate designs, respectively, and has an average error rate of 10%, while the approximate CMOS MUL has an average error rate of 13%, and requires at least 64% less chip real-estate., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

By their very nature, voltage/current excited Spin Waves (SWs) propagate through waveguides without consuming noticeable power. If SW excitation is performed by the continuous application of voltages/currents to the input, which is usually the case, the overall energy consumption is determined by the transducer power and the circuit critical path delay, which leads to high energy consumption because of SWs slowness. However, if transducers are operated in pulses the energy becomes circuit delay independent and it is mainly determined by the transducer power and delay, thus pulse operation should be targeted. In this paper, we utilize a 3-input Majority gate (MAJ) to investigate the Continuous Mode Operation (CMO), and Pulse Mode Operation (PMO). Moreover, we validate CMO and PMO 3-input Majority gate by means of micromagnetic simulations. Furthermore, we evaluate and compare the CMO and PMO Majority gate implementations in term of energy. The results indicate that PMO diminishes MAJ gate energy consumption by a factor of 18. In addition, we describe how PMO can open the road towards the utilization of the Wave Pipelining (WP) concept in SW circuits. We validate the WP concept by means of micromagnetic simulations and we evaluate its implications in term of throughput. Our evaluation indicates that for a circuit formed by four cascaded MAJ gates WP increases the throughput by 3.6x., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of The FA 1 Majority and 2 XOR gates, which outputs Sum and Carry-out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Spin Hall Effect (SHE), Domain Wall Motion (DWM), and Spin-CMOS implementations. Our evaluation indicates that the proposed SW FA consumes 22.5% and 43% less energy than the direct SW gate based and 22nm CMOS counterparts, respectively. Moreover it exhibits a more than 3 orders of magnitude smaller energy consumption when compared with state-of-the-art MTJ, SHE, DWM, and Spin-CMOS based FAs, and outperforms its contenders in terms of area by requiring at least 22% less chip real-estate., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

Spin waves modes in magnetic waveguides with width down to 320 nm have been studied by electrical propagating spin-wave spectroscopy and micromagnetic simulations for both longitudinal and transverse magnetic bias fields. For longitudinal bias fields, a 1.3 GHz wide spin-wave band was observed in agreement with analytical dispersion relations for uniform magnetization. However, transverse bias field led to several distinct bands, corresponding to different quantized width modes, with both negative and positive slopes. Micromagnetic simulations showed that, in this geometry, the magnetization was nonuniform and tilted due to the strong shape anisotropy of the waveguides. Simulations of the quantized spin-wave modes in such nonuniformly magnetized waveguides resulted in spin wave dispersion relations in good agreement with the experiments., Comment: 11 pages, 5 figures. This work has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" - CHIRON

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave logic gates, and 16nm and 7nm CMOS. The results demonstrate that the proposed structures provide energy reduction of 25%-50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction between 43x and 0.8x when compared to the 16nm and 7nm CMOS while having delay overhead between 11x and 40x., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

The characteristics of confined magnetoelastic waves in nanoscale ferromagnetic magnetostrictive waveguides have been investigated by a combination of analytical and numerical calculations. The presence of both magnetostriction and inverse magnetostriction leads to the coupling between confined spin waves and elastic Lamb waves. Numerical simulations of the coupled system have been used to extract the dispersion relations of the magnetoelastic waves as well as their mode profiles., Comment: 30 pages, 9 figures

By their very nature, Spin Waves (SWs) with different frequencies can propagate through the same waveguide without affecting each other, while only interfering with their own species. Therefore, more SW encoded data sets can coexist, propagate, and interact in parallel, which opens the road towards hardware replication free parallel data processing. In this paper, we take advantage of these features and propose a novel data parallel spin wave based computing approach. To explain and validate the proposed concept, byte-wide 2-input XOR and 3-input Majority gates are implemented and validated by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. Furthermore, we introduce an optimization algorithm meant to minimize the area overhead associated with multifrequency operation and demonstrate that it diminishes the byte-wide gate area by 30% and 41% for XOR and Majority implementations, respectively. To get inside on the practical implications of our proposal we compare the byte-wide gates with conventional functionally equivalent scalar SW gate based implementations in terms of area, delay, and power consumption. Our results indicate that the area optimized 8-bit 2-input XOR and 3-input Majority gates require 4.47x and 4.16x less area, respectively, at the expense of 5% and 7% delay increase, respectively, without inducing any power consumption overhead. Finally, we discuss factors that are limiting the currently achievable parallelism to 8 for phase based gate output detection and demonstrate by means of OOMMF simulations that this can be increased 16 for threshold based detection based gates., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

This paper provides a tutorial overview over recent vigorous efforts to develop computing systems based on spin waves instead of charges and voltages. Spin-wave computing can be considered as a subfield of spintronics, which uses magnetic excitations for computation and memory applications. The tutorial combines backgrounds in spin-wave and device physics as well as circuit engineering to create synergies between the physics and electrical engineering communities to advance the field towards practical spin-wave circuits. After an introduction to magnetic interactions and spin-wave physics, all relevant basic aspects of spin-wave computing and individual spin-wave devices are reviewed. The focus is on spin-wave majority gates as they are the most prominently pursued device concept. Subsequently, we discuss the current status and the challenges to combine spin-wave gates and obtain circuits and ultimately computing systems, considering essential aspects such as gate interconnection, logic level restoration, input-output consistency, and fan-out achievement. We argue that spin-wave circuits need to be embedded in conventional CMOS circuits to obtain complete functional hybrid computing systems. The state of the art of benchmarking such hybrid spin-wave--CMOS systems is reviewed and the current challenges to realize such systems are discussed. The benchmark indicates that hybrid spin-wave--CMOS systems promise ultralow-power operation and may ultimately outperform conventional CMOS circuits in terms of the power-delay-area product. Current challenges to achieve this goal include low-power signal restoration in spin-wave circuits as well as efficient spin-wave transducers., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" - CHIRON

The key enabling factor for Spin Wave (SW) technology utilization for building ultra low power circuits is the ability to energy efficiently cascade SW basic computation blocks. SW Majority gates, which constitute a universal gate set for this paradigm, operating on phase encoded data are not input output coherent in terms of SW amplitude, and as such, their cascading requires information representation conversion from SW to voltage and back, which is by no means energy effective. In this paper, a novel conversion free SW gate cascading scheme is proposed that achieves SW amplitude normalization by means of a directional coupler. After introducing the normalization concept, we utilize it in the implementation of three simple circuits and, to demonstrate its bigger scale potential, of a 2-bit inputs SW multiplier. The proposed structures are validated by means of the Object Oriented Micromagnetic Framework (OOMMF) and GPU-accelerated Micromagnetics (MuMax3). Furthermore, we assess the normalization induced energy overhead and demonstrate that the proposed approach consumes 20% to 33% less energy when compared with the transducers based conventional counterpart. Finally, we introduce a normalization based SW 2-bit inputs multiplier design and compare it with functionally equivalent SW transducer based and 16nm CMOS designs. Our evaluation indicate that the proposed approach provided 26% and 6.25x energy reductions when compared with the conventional approach and 16nm CMOS counterpart, respectively, which demonstrates that our proposal is energy effective and opens the road towards the full utilization of the SW paradigm potential and the development of SW only circuits., Comment: This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" CHIRON

This paper discusses the physics of magnetoelasticity and magnetoelastic waves as well as their mathematical description. Magnetoelastic waves occur as a result of strong coupling between spin waves and elastic waves in magnetostrictive ferromagnetic media. In a first part, the basic behavior of spin waves is reviewed in both bulk ferromagnets as well as in thin films. Next, elastic waves are discussed with a focus on thin films. Finally, the interactions between the elastic and magnetic domains are described and it is shown how this results in the formation of magnetoelastic waves. Based on the description of bulk magnetoelastic waves, a theory for magnetoelastic waves in thin films is developed and their dispersion relations are derived. It is shown that the behavior strongly depends on the geometry of the system, especially on the polarization of spin and elastic waves and the direction of the magnetization of the magnetostrictive ferromagnet., Comment: 40 pages, 7 figures

The characteristics of spin waves in ferromagnetic waveguides with nonuniform magnetization have been investigated for situations where the shape anisotropy field of the waveguide is comparable to the external bias field. Spin-wave generation was realized by the magnetoelastic effect by applying normal and shear strain components, as well as by the Oersted field emitted by an inductive antenna. The magnetoelastic excitation field has a nonuniform profile over the width of the waveguide because of the nonuniform magnetization orientation, whereas the Oersted field remains uniform. Using micromagnetic simulations, we indicate that both types of excitation fields generate quantised width modes with both odd and even mode numbers as well as tilted phase fronts. We demonstrate that these effects originate from the average magnetization orientation with respect to the main axes of the magnetic waveguide. Furthermore, it is indicated that the excitation efficiency of the second-order mode generally surpasses that of the first-order mode due to their symmetry. The relative intensity of the excited modes can be controlled by the strain state as well as by tuning the dimensions of the excitation area. Finally, we demonstrate that the nonreciprocity of spin-wave radiation due to the chirality of an Oersted field generated by an inductive antenna is absent for magnetoelastic spin-wave excitation., Comment: This work was funded through the FETOPEN-01-2016-2017-FET-Open research and innovation actions (CHIRON project: Grant Agreement No. 801055). F.V. acknowledges financial support from the Research Foundation-Flanders (FWO) through grant No. 1S05719N