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In recent years, field-programmable gate arrays (FPGAs) have been increasingly deployed in datacenters as programmable accelerators that can offer software-like flexibility and custom-hardware-like efficiency for key datacenter workloads. To improve the efficiency of FPGAs for these new datacenter use cases and data-intensive applications, a new class of reconfigurable acceleration devices (RADs) is emerging. In these devices, the FPGA fine-grained reconfigurable fabric is a component of a bigger monolithic or multi-die system-in-package that can incorporate general-purpose software-programmable cores, domain-specialized accelerator blocks, and high-performance networks-on-chip (NoCs) for efficient communication between these system components. The integration of all these components in a RAD results in a huge design space and requires re-thinking the implementation of applications that need to be migrated from conventional FPGAs to these novel devices. In this work, we introduce RAD-Sim, an architecture simulator that allows rapid design space exploration for RADs and facilitates the study of complex interactions between their various components. We also present a case study that highlights the utility of RAD-Sim in re-designing applications for these novel RADs by mapping a state-of-the-art deep learning (DL) inference FPGA overlay to different RAD instances. Our case study illustrates how RAD-Sim can capture a wide variety of reconfigurable architectures, from conventional FPGAs to devices augmented with hard NoCs, specialized matrix-vector blocks, and 3D-stacked multi-die devices. In addition, we show that our tool can help architects evaluate the effect of specific RAD architecture parameters on end-to-end workload performance. Through RAD-Sim, we also show that novel RADs can potentially achieve $2.6\times $ better performance on average compared to conventional FPGAs in the key DL application domain.

Abstract Spinal metastases often occur in the advanced stages of breast, lung or prostate cancer, resulting in a significant impact on the patient’s quality of life. Current treatment modalities for spinal metastases include both systemic and localized treatments that aim to decrease pain, improve mobility and structural stability, and control tumour growth. With the development of non-toxic photosensitizer drugs, photodynamic therapy (PDT) has shown promise as a minimally invasive non-thermal alternative in oncology, including for spinal metastases. To apply PDT to spinal metastases, predictive algorithms that optimize tumour treatment and minimize the risk of spinal cord damage are needed to assess the feasibility of the treatment and encourage a broad acceptance of PDT in clinical trials. This work presents a framework for PDT modelling and planning, and simulates the feasibility of using a BPD-MA mediated PDT to treat bone metastases at two different wavelengths (690 nm and 565 nm). An open-source software for PDT planning, PDT-SPACE, is used to evaluate different configurations of light diffusers (cut-end and cylindrical) fibres with optimized power allocation in order to minimize the damage to spinal cord or maximize tumour destruction. The work is simulated on three CT images of metastatically involved vertebrae acquired from three patients with spinal metastases secondary to colorectal or lung cancer. Simulation results show that PDT at a 565 nm wavelength has the ability to treat 90% of the metastatic lesion with less than 17% damage to the spinal cord. However, the energy required, and hence treatment time, to achieve this outcome with the 565 nm is infeasible. The energy required and treatment time for the longer wavelength of 690 nm is feasible ( $${\sim }\,40$$ ∼ 40 min), but treatment aimed at 90% of the metastatic lesion would severely damage the proximal spinal cord. PDT-SPACE provides a simulation platform that can be used to optimize PDT delivery in the metastatic spine. While this work serves as a prospective methodology to analyze the feasibility of PDT for tumour ablation in the spine, preclinical studies in an animal model are ongoing to elucidate the spinal cord damage extent as a function of PDT dose, and the resulting short and long term functional impairments. These will be required before there can be any consideration of clinical trials.

Contemporary datacenters are enhancing their compute capacity, power efficiency, and processing latency by integrating field-programmable gate arrays (FPGA). One would like to virtualize FPGAs to share them between multiple users and to be able to allocate incoming tasks to FPGAs without interrupting their operation. To virtualize FPGAs, their complexities, such as board-specific system-level integration and tricky I/O timing closure problems should be abstracted away from users. To this end FPGA designers have proposed the shell concept which abstracts away the board-specific details from the user and provides an easy-to-use interface to the user application. In this paper, we create several shells using a wide variety of interconnect solutions and rigorously evaluate them in terms of accelerator frequency, usable bandwidth, area-efficiency, latency, wire demand, and FPGA routing congestion. We show that virtualization of four accelerators per chip with traditional bus-based FPGA interconnect costs an average frequency drop of 24%, increases the wire demand of the shell to 2.78X, and creates significant routing congestion. We also show that while FPGA-optimized soft network on chip interconnect solutions can mitigate the reduction in accelerator frequency, they exacerbate the wire demand and routing congestion problems and offer a lower usable bandwidth. Finally, we demonstrate that hard networks on chip are a superior interconnect solution for virtualized FPGAs in all of the aforementioned evaluation criteria making them well-suited to datacenteroptimized FPGAs.