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Direct-RF analog-to-digital conversion has been an active research topic for many years. Recent technology and design advances have pushed these data converters from research to real-world deployment. We will discuss requirements and implementation of such an ADC, designed for direct-RF conversion in a wireless base-station.

A 13bit 5GS/s time-interleaved ADC is described which uses a chopping technique to reduce the effect of interleaved flicker noise spectral artefacts and to increase the ADC immunity to input signal characteristics. Enhanced offset and time-skew calibration algorithms are developed to maximize the performance in the presence of non-ideal sampling switches. At 5GS/s, the ADC dissipates 641mW while achieving a 62dB and 57dB of SFDR and SNDR respectively while maintaining a SFDR excluding HD2 and HD3 better than 70dBc across the first Nyquist band for input amplitudes down to −20dBFS.

This work presents direct-RF TX/RX modular tiles for monolithic integration in 16nm FinFET. The TX tile embeds 4 baseband-to-RF signal chains with 14-bit 9GS/s DACs while the RX tile provides 2 RF-to-baseband signal chains with 13-bit 4.5GS/s ADCs. Each tile includes a low-noise PLL [1] and can support full Nyquist bandwidth. The TX path demonstrates better than −67dBc ACPR when synthetizing a half-loaded band 42 and consumes 700mW. The RX path shows an EVM of 11.6% for the in-band blocking test of the 3.5GHz band and consumes 747mW. These tiles have been integrated in a 372mm2 FPGA SoC and demonstrate better than 90dB digital-to-analog isolation and sub-80ps channel alignment.

O progresso tecnológico é um importante fator do desenvolvimento económico. As tecnologias de informação têm evoluído de uma forma significativa, influenciando, de modo mais ou menos homogéneo todos os setores. O setor da construção não é exceção, mas enfrenta alguns desafios tecnológicos, nomeadamente no uso de software dissociados, o que se traduz num entrave à produtividade do setor. O BIM surge assim como uma aplicação tecnológica que procura responder a este problema, permitindo uma maior interação entre todos os intervenientes, uma melhor execução de projetos mais complexos, a antecipação de conflitos evitando possíveis erros e omissões e ainda um melhor planeamento e controlo das obras. Este artigo tem por objetivo apresentar um estudo de como a modelação e interação entre as especialidades modeladas, influi na gestão do projeto, nomeadamente na gestão de colisões, bem como de criar um procedimento que permita automatizar o processo de planeamento. No âmbito do desenvolvimento deste projeto, o caso prático selecionado, foi um Edifício multifamiliar em Cascais, onde foi efetuada a modelação tridimensional do mesmo, seguindo-se uma análise 4D e 5D, em MS Project e Autodesk Navisworks e, por fim, a automatização do processo de planeamento, que foi desenvolvida através de programação em Dynamo.

In this paper, we present a Programmable SoC device with monolithically integrated RF-ADCs and RF-DACs in a 16nm FinFET process. The device includes quad ARM Cortex-53 and dual ARM Cortex-R5 processing subsystem, 750K programmable logic cells, 4000 DSP slices and 4 32Gb/s serial transceivers. Each 14-bit RF-DAC operates at a sample rate of up to 6.4GS/s and can directly synthesize RF carriers up to 4GHz. Each 12-bit RF-ADC operates at a sample rate of up to 4GS/s and can directly digitize RF carriers up to 4GHz. Other RF functions generally associated with analog / RF such as complex mixing and filtering have also been integrated and implemented in the digital domain (digital-RF), enabling lower system cost and power and increased flexibility.

In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1–4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck. In this work, a three-stage asynchronous pipelined-SAR with open-loop integrator-based amplifiers is used to maximize the sampling frequency, resolution and linearity. The solution is mostly supported by dynamic circuits and multiple calibration loops to reduce cost, power and noise, maximize process portability and support production testability.

Dissertação de mestrado integrado em Engenharia Ciivil, As tecnologias de informação têm evoluído de forma significativa, influenciando, de forma mais ou menos homogénea, todos os setores. O setor da construção não é exceção, mas enfrenta alguns desafios tecnológicos, nomeadamente no uso de software separado, que se traduz num entrave à produtividade do setor (Martins, 2009). O BIM surge como uma aplicação tecnológica que procura responder a este problema, permitindo uma maior interação entre todos os intervenientes, uma melhor execução de projetos especialmente complexos, a antecipação de conflitos evitando possíveis erros e omissões e ainda um melhor planeamento e controlo de obras. Num mercado cada vez mais competitivo, as empresas de construção necessitam de automatizar tarefas e processos, bem como de métodos mais eficientes, em particular nas fases em que a rapidez e eficácia de troca de informações é essencial, como é o caso da fase do planeamento. Nesta dissertação, será apresentado um conjunto de ferramentas de planeamento e gestão que tem como objetivo controlar o tempo e o custo ao longo da construção, e a integração destas com o BIM 4D e 5D. Como exemplo prático, modelou-se um edifício multifamiliar em Revit, nomeado de “Edifício 25 de Abril”, situado em Cascais. Foram modeladas as especialidades de Arquitetura e Estruturas, onde se aplicou o clash-detection e realizou o faseamento construtivo. Efetuou-se ainda, uma análise temporal, Instante 1 e Instante 2, entre o modelo tridimensional, o planeamento do projeto e o custo da construção, a partir da integração dos softwares, Revit (Dynamo) e Excel. E obteve-se, como resultado, modelos coloridos para o Instante 1 e Instante 2, onde é possível aferir o estado e o custo da construção. A adoção da metodologia BIM permitiu a agregação de várias informações relevantes ao desenvolvimento do projeto, potenciando a antecipação de possíveis problemas em obra, como por exemplo a compatibilização ou erros nos projetos, e ainda um conjunto de ferramentas que permitirão uma gestão de tempos e custos durante a construção., Information technologies have evolved significantly, influencing, in a more or less homogeneous way, all sectors. The construction sector is no exception, but faces some technological challenges, namely in the use of separate software, which translates into an obstacle to the productivity of the sector. The BIM (Building Information Modeling) comes up as a technology trying to answer this problem. It consists of a collaborative and multidisciplinary development process, where a digital model is obtained with all the information from each party involved in the project, throughout the whole project lifecycle. In an ever more competitive market, construction companies need automation and computerization of tasks and processes, as well as more efficient methods in phases, where the speed and efficiency of information exchange is essential, as is the case with the planning phase. In this thesis, a set of planning and management tools will be presented, with the objective of controlling the time and cost, and the integration of these with BIM 4D and 5D. As a practical example, a multi-family building was modelled in Revit, named “Edifício 25 de Abril”, located in Cascais. Two specialties were modelled, Structure and Architecture, the clash-detection and constructive phasing were applied to the model. Time-analysis Instant 1 and Instant 2 were conducted between the three-dimensional model and the project planning, starting on the integration of multiple software, Revit (Dynamo) and Excel. As a result, colored models for Instants 1 and 2 were created, where it is possible to observe the state and cost of the construction at Instants 1 and 2 relative to the project planning. It is understood then that the use of the BIM methodology in scope of this thesis, allowed the aggregation of information relevant to the project development of the project, the potential to anticipate possible construction issues, as an example, the compatibility or project errors, in addition to a set of tools that allow the time and cost management throughout the construction lifecycle.

Since the 1970's, the analog switches in switched-capacitor (SC) circuits are operated by nonoverlapping bi-phase control signals (/spl phi//sub 1/, /spl phi//sub 2/). The nonoverlapping of these two phases is essential for successful SC operation since, a capacitor inside an SC circuit can discharge if two switches, driven by /spl phi//sub 1/ and /spl phi//sub 2/, are turned on simultaneously. Moreover, since 1983, two additional phases are generally used in many SC circuits, which consist of advanced versions of /spl phi//sub 1/ and /spl phi//sub 2/. These two additional phases overcome the problem of signal-dependent charge injection. This paper presents a low-power and low-voltage analog-to-digital (A/D) interface module for biomedical applications. This module provides an A/D conversion based on a mixed clock-boosting/switched-opamp (CB/SO) second-order sigma-delta (/spl Sigma//spl Delta/) modulator, capable of interfacing with several different types electrical signals existing in the human body, only by re-programming the output digital filter. The proposed /spl Sigma//spl Delta/ architecture employs a novel single-phase scheme technique, which improves the dynamic performance and highly reduces the clocking circuitry complexity, substrate noise and area. Simulated results demonstrate that the signal integrity can be preserved by exploring the gap between the high conductance region of pMOS and nMOS switches at low power-supply voltages and the fast clock transitions that exist in advanced CMOS technologies. The mixed CB/SO architecture together with the overall distortion reduction resulting from using the proposed single-phase scheme, result that the dynamic range of the modulator is pushed closer to the theoretical limit of an ideal second-order /spl Sigma//spl Delta/ modulator.

Se outrora o manual escolar era o único recurso disponível nas escolas, atualmente a sua utilização entra em competição com os recursos digitais, mais apelativos e dinâmicos. Estudos existentes demonstram a importância na utilização de ambos os recursos, existindo defensores e críticos para o seu uso. Este relatório não pretendeu entrar nessa discussão, mas refletiu acerca da importância do manual escolar para o professor e para o aluno do 3º Ciclo do Ensino Básico. Na minha anterior experiencia como docente nunca tinha recorrido à utilização de recursos digitais. Deste modo e no âmbito do estágio realizado em duas escolas diferentes e depois de atribuídas as turmas para Geografia e História, optou-se pela lecionação das turmas do 8º ano através do manual escolar, ao passo que as turmas do 9º ano foram lecionadas através de recursos digitais. No final do estágio pude constatar que a utilização de recursos digitais revelou-se proveitosa na transmissão de conhecimentos aos alunos (à semelhança do manual escolar), mas requereu bastante tempo para a sua construção. Foram ainda aplicados 88 inquéritos aos alunos e não obstante os resultados demonstrarem uma ligeira tendência preferencial para a utilização de recursos digitais, a relação estabelecida com o professor e o sucesso na avaliação são aspetos capazes de persuadir essa preferência.

This paper describes and compares some of the most energy and area efficient self-calibration techniques reported over the past years. Additional techniques used to further improve power dissipation are briefly described as well. A robust mixed-signal self-calibration technique is proposed, in which, the multi-bit first stage in the ADC is calibrated without requiring any modifications, as long as the ideal conversion characteristic of this stage is known. A novel Gaussian Noise Generator is used as the input analog stimulus and, on the digital side, the calibration algorithm does not require explicit multiplications, which greatly simplifies the digital circuitry. Experimental measurements of a 13-bit ADC fabricated in 90 nm CMOS, after calibration and at 40 MS/s, show that the SFDR is improved by over 14 dB (to 84 dB), the THD is improved by over 10 dB (to −80 dB), achieving a peak ENOB of 11.3 bits for a 10 MHz input and with a 1.2 V power supply.

A 2nd-order DeltaSigma ADC implemented in 0.18mum CMOS occupies 0.06mm2 and dissipates 0.2mW from a 0.9V supply. It achieves 80dB SNDR and 83dB DR over a 10kHz BW employing a single-phase technique to reach such performance. An amplifier-sharing scheme is proposed to improve power and area efficiency

A 1.5V 10-b 4MS/s pipeline ADC for sensor interfacing is described. Amplifiers are efficiently shared between stages and low-voltage techniques are used to reduce the power supply down to 1.4V. The selected resolution-per-stage greatly simplifies the implementation of a low-power design. Simulated results using a standard digital 0.18 /spl mu/m CMOS technology exhibit 9.5 effective bits at Nyquist-rate. The chip occupies 0.6 mm/sup 2/ and dissipates only 3 mW at maximum conversion-rate.

A novel single phase scheme for use in switched-capacitor (SC) circuits is described. Signal integrity is preserved by exploring the gap between the high conductance region of PMOS and NMOS switches at low power-supply voltages and the fast clock transitions that exist in advanced CMOS technologies. In order to illustrate the attractiveness of the proposed scheme, two practical circuit examples are presented. Electrical simulated results of a low-voltage 2/sup nd/-order /spl Sigma//spl Delta/ modulator clearly demonstrate the improvements in terms of harmonic distortion that can be achieved using this technique.

The design of a 1.8 V, 10-bit, 130+MS/s, 2-channel pipeline ADC in a 0.18 μm CMOS technology is described. A new hybrid low-voltage pipeline architecture that combines the best advantages of the Switched-Opamp (SO) and of the clock-bootstrapped (CB) techniques is proposed in this paper. This new low-voltage implementation has the capability to reduce the number of switches in the switched-capacitor blocks and, at the same time, the number of required clock-bootstrapped circuits, improving the overall linearity and the active silicon area. The ADC architecture is tailored using a design methodology for optimization based on genetic algorithms. The adopted resolution per stage avoids the need of scaling the stages, simplifying the design of a low-power design.