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The decoder is an integral part of modern memory, processors. In this work, a 5 to 32 and 6 to 64 decoders have been designed and characterized using low-order decoders for the state-of-the-art digital systems. The Design and Synthesis work have been executed at the Register Transfer Level (RTL) and the Testbench based Verification has been performed to ensure the functional correctness of the designs with timing constraints. RTL Coding is done at VerilogHDL Std. IEEE 1364-2001 and IEEE 1364-2005. It is observed that the 5 to 32 and 6 to 64 order decoders utilize the highest 15% and 30% bonded IOBs where the 2 to 4 decode 2% only. It is found that the 6 to 64 decoders have 5% higher delay to 5 to 32 decoders whereas the 5 to 32 decoder has 5.5% more logic delay and 9.1% less route delay as compared to the 6 to 64 decoders. [ABSTRACT FROM AUTHOR]

The need to transfer the primary data conversions close to the sensors, to the endpoints of monitoring systems, as well as in IoT terminal devices makes the development of new approaches to computing and the design of appropriate algorithms relevant. The article shows stream processing algorithms that provide functional transformations of signals presented in bit stream form (single pulse streams, PWM signal streams) and binary codes at the same time. In such algorithms, the computational process is based on discretization, pulse frequency sweep and pulse-width sweep of codes as well as organization of parallel-serial processing. The suggested principles of algorithm organization are based on the fact that the computation is considered not as an event associated with calculation but as a continuous process of a result formation. The transition to algorithmic representations proposed by the authors makes it possible to obtain universal behavioral descriptions, independently of the specific hardware on which their implementation is performed. [ABSTRACT FROM AUTHOR]

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Abstract: Fingerprint recognition is one of the most popular methods used by Biometric identification systems for personnel identification. CORDIC algorithm provides wonderful solution to perform the math intensive operations at the cost of few components like adder, shifter, multiplexer.Etc. Such math intensive operations are required to perform during the image enhancement phase of finger print recognition process. In this paper CORDIC based architecture is proposed to evaluate almost all the trigonometric functions. This is implemented using XILINX ISE 13.2. Performance of the architecture is analyzed in terms of relative error. [Copyright &y& Elsevier]

The work focuses on the design and implementation of a field programmable gate array (FPGA) based voltage controller for a single-phase voltage source inverter (VSI) with an inductance-capacitance (L-C) filter. The control algorithm of the open loop and closed loop control schemes of the controller are designed using hardware descriptive languages (VHDL and VerilogHDL) and are implemented using Xilinx SPARTAN 3E FPGA. The sinusoidal pulse-width modulation (SPWM) technique is utilised to realise the controller with a provision to change the modulation index in response with varying load conditions. Suitable L-C filter is designed to minimise the undesirable frequency components in the output voltage. The efficacy of the proposed control schemes in FPGA is validated via successful interface with a prototype VSI and the experimental verification of the controllers are carried out under different loading conditions. [ABSTRACT FROM AUTHOR]