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This article introduces a paradigm shift in radar technology with field programmable gate array (FPGA)-driven Phase estimation using floating point arithmetic (FPA). Leveraging FPGA's parallel processing and the precision of FPA, this work promises enhanced accuracy and efficiency. The proposed system's key performance metrics include the following: number of slices: 20,941, number of look-up tables (LUTs): 22,371, number of digital signal processing (DSP) blocks: 2, delay: 112.9 ns, and power consumption: 7.2 mw. A comparative analysis showcases advantages in area utilization, LUT, and DSP blocks despite a trade-off with delay. The presented methodology and results demonstrate the feasibility of real-time phase estimation at GHz rates, positioning this approach as transformative for next-gen radar systems. [ABSTRACT FROM AUTHOR]

To replace the field-programmable gate array semiconductors used in the defense satellite industry, we conducted a technical investigation of application-specific integrated circuit (ASIC) semiconductors. The analysis results show that ASIC semiconductors have the heat dissipation, reliability, and radiation resistance capabilities required in a space environment and excellent performance indicators related to the resolution of synthetic aperture radar payloads, such as operating frequency. Research and development of mission-customized ASIC semiconductors that fit the requirements for NSP(new-space paradigm) should be preceded to expanse bases of the space industry, national security capabilities for next-generation space deveolpment also to secure competitiveness of technology and domestic supply chain as space parts itselfs.

Power estimation has a major impact on the reliability of very-large-scale integration (VLSI) circuits. As a results power estimation is highly needed in VLSI circuits at the early stages. One of the evident challenges in integrated circuit (IC) industry is development and investigation of techniques for the reduction of design complexity due to the growing process variations and reduction of chip manufacturing turnaround time. Under these conditions, the higher design levels of average power estimation before the chip manufacturing process is highly essential for the calculation of power budget and to take the necessary steps for the reduction of power consumption. Over the years, most of the approaches were designed to estimate the power usage, however, most of the conventional techniques are time consuming, resource-intensive and largely manual. Machine learning techniques have received much attention in many of the engineering applications and are capable for modelling the complex systems through historical data. Hence, in this work on chip-based power estimation for complementary metaloxide-semiconductor (CMOS) VLSI using support-vector machine (SVM) is presented to estimate the power. The SVM is employed to estimate the usage of power at runtime. The performance of this model is evaluated in terms of Power usage, delay, data accuracy and error rate. [ABSTRACT FROM AUTHOR]

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP. [ABSTRACT FROM AUTHOR]

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

Internet of Medical Things (IoMT) is the combination of medical devices and utilization by networking technologies. But, the response time and cost were not reduced. In order to address these issues, IoMT Aware Data Collective Quadratic Ensembled Cat Boost Module Classification (IoMT-DCQECBMC) Method is introduced. Initially, IoMT Aware Data Collection is used for gathering data from medical devices. After the data collection process, Quadratic Ensembled Cat Boost Module Classification (QECBM) is carried out in IoMT-DCQECBMC Method to design an efficient VLSI architecture with minimal cost and area. The quadratic classifier is considered the weak learner that categorizes the module for efficient VLSI design. Finally, the weak learners are joined to form the strong classifier to perform non-invasive blood glucose monitoring efficiently. Experimental evaluation is carried out on the factors such as computation cost, area, and accuracy with respect to a number of modules in VLSI circuits. The accuracy of the IoMT-DCQECBMC method is increased by 4% than conventional methods. In addition, the area consumption and computation cost of the proposed IoMT-DCQECBMC method are reduced by 13% to 30% other than existing methods. [ABSTRACT FROM AUTHOR]