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Groundwater is a vital resource that provides drinking water to over half of the world's population. However, groundwater contamination has become a serious issue due to human activities such as industrialization, agriculture, and improper waste disposal. The impacts of groundwater contamination can be severe, including health risks, environmental damage, and economic losses. In this research work a list of unknown groundwater contamination sources were developed for the Wang-Tien landfill using Groundwater Modeling System (GMS). Further, AI based models have been developed which accurately predicts the contamination from the sources at this site. A serious complication with most previous studies using Artificial Neural Network (ANN) for contamination source identification has been the large size of the neural networks. To simplify this, we have designed the ANN models which use three different ways of presenting inputs that are categorized by hierarchical k-means clustering. Such an implementation reduces the overall complexity of the model along with high accuracy. The predictive capability of developed models was assessed using performance indices and compared with the ANN models. The results show that the Hybrid model of hierarchical K-means Clustering and ANN model (HCA-ANN) is highly accurate model for identifying pollution sources in contaminated water.

The research work presents a smaller size rectangular mirco-strip patch antenna. In this work, a smaller size patch antenna designed using meta-material. In the work, antenna’s resonate frequency is 1.815 GHz, normally designing a rectangular mirco-strip patch antenna at this frequency required more space but with the help of meta-material minimize the size of patch and also base structure of the antenna. The designed antenna is fit when required less size antenna, at 1.815 GHz frequency.

For saving human life and wildlife, methods of fire safety need to be implemented in different areas like house hold, industries, forests etc. Algorithms of image processing have been developed over the years for fire detection. Such algorithms have been discussed here. Although these algorithms are able to detect fire but unable to differentiate between fire and orange color. In our proposed method, we developed a discrimination algorithm to differentiate between fire and orange color. This algorithm is applied on the detected fire pixels to check whether they are fire pixels or orange color pixels.

With the aggressive scaling trend in the VLSI technology the NBTI effect has emerged as a major reliability concern for both CMOS as well as FinFET based circuits. NBTI causes an incremental deviation in the threshold voltage of PMOS and hence causes variation in performance and timing of digital circuits. This timing mismatch is a serious issue for synchronous clock based circuits such as dynamic logic gates. Further NBTI may increase the delay of circuits which are lying in the critical path of a system and may lead to failure of system. This NBTI caused delay can be a serious issue for wide fan-in dynamic OR gate lying in the critical path of a high speed microprocessor. In this work the impact of NBTI on the FinFET based wide fan-in dynamic OR gate has been analysed. A novel sensor based NBTI tolerant FinFET dynamic logic OR gate has also been proposed here to overcome any degradation in performance due to NBTI. Proposed design makes use of double gate FinFET back gate biasing technique to maintain a constant threshold voltage of the transistors under NBTI degradation. Proposed design is capable of maintaining a stable performance of dynamic OR gate with only 1.8 % variation in delay for a lifetime of 10 years.

Limited energy consumption in multimedia requires very low power circuits. Performance of SRAM in circuit affects the system, therefore power consumption of SRAM needs to be reduced. Many techniques have been proposed to minimize the leakage current, however they have not been able to reduce significantly. In this paper we have mainly focused on the reduction of Leakage Current in SRAM Cell. A leakage reduction technique has been proposed and implemented on 8T FinFET Based SRAM cell. Effect of NBTI is also observed on the proposed cell. The Simulation has been performed on H Spice at 32nm technology.

To make portable battery operated devices moreefficient with low leakage current is a major challenge with the technology scaling. The power dissipation is expected to increase further in next generation technologies because of the exponential increase in leakage currents with technology scaling. FinFET device was introduced as a suitable replacement of CMOS due to its reduced short channel effects at lower technology nodes. However, leakage current still remains comparable to device ONcurrent at highly scaled technology nodes. Continuous voltage supply to retain the data in SRAM cell contributes a major part of leakage current in any processor design. This paper proposed a novel circuit technique to reduce the leakage current and power consumption of SRAM cell. The proposed design achieves a very high reduction in static power dissipation, up to 4% reduction in read power and upto 49% reduction in write power dissipation as compared to conventional FinFET 6T SRAM cell. All the HPSICE simulation is performed using 32nm BSIM technology file.

The conventional NOR-based decoders are one ofthe fastest dynamic decoder circuits employed in microprocessors. However, they suffer from a huge amount of power dissipationresulting from the presence of short circuit paths betweenthe supply and the ground through pull-down network. Twodecoder designs with a novel selective precharge circuit have beenproposed in this paper using 32nm FinFET technology. The firstdesign is based on CG-FinFET and the second design is basedon IG-FinFET. The average power consumption gets reducedby 93% at the cost of a little increase in delay from 12.3ps to19.9ps for CG-FinFET based design and from 12.3ps to 22.70psfor IG-FInFET based design. By operating the FinFET devicesin independent gate mode, the variations in delay of the circuitdue to process variation effects are suppressed. The standarddeviation in delay gets reduced by 68.8% after reverse biasingthe PFinFET and NFinFET back gate. This is achieved at thecost of a negligible increase in delay. The leakage of the circuitgets reduced by 11.26% due to reverse bias on the back gate. The circuits have been simulated using 2000 Monte Carlo runsin HSPICE simulator at 1GHz clock pulse.

Efficient and process variation tolerant memory isthe current market demand especially for Portable devices. Inscaled down devices leakage current becomes comparable to theOn-State current. SRAM Cell remains in stand-by mode for mostof the time and accounts for maximum average power dissipation. This research work explores the existing built-in feedback andback gate biasing techniques and proposes a 7T IG-FinFET basedSRAM Topology which addresses the aforementioned issues. This7T FinFET based SRAM Topology has been used with readdecoupling which shows 44% increase in Read Noise Marginwhen compared to conventional 6T SG-FinFET based SRAM. Further, device sizing and back gate biasing along with built-infeedback is incorporated which saves 73 % power during standbymode and is process variation tolerant.

Leakage power dissipation, timing delay and high noise immunity in advanced embedded static random access memories cells are main critical issues in low power battery operated devices. The newly proposed FinFET based highly noise immune Power gated 6T SRAM design is targeting these areas and successfully suppress leakage power dissipation with maintaining stability of data in standby mode. A single ended read and write assist circuitry is also presented to here, which enhancing read and write noise margin for maintaining robustness of SRAM stability. As compared with conventional FinFET SRAM designs in the proposed design, the power dissipation in SLEEP mode is reduced up to 86.8% and, read and write power consumption are up to 98.9% and 16.5%, respectively. The noise margin of proposed design is increased up to 45× as compared to self-reverse biased power gated SRAM at 32nm technology node.

Wide Fan-in dynamic OR gate has always been an integral part of high speed microprocessors. But dynamic logic gate suffers from low noise immunity. A weak PMOS keeper was introduced to increase the noise immunity. Keeper technique acts as a compensatory mechanism for charge loss due to leakage current and maintains high noise immunity while allowing leakage current through dynamic gate. A large size keeper is used for wide fan-in dynamic OR gate which allows large leakage current through the dynamic gate. This large leakage current unnecessarily results in large power dissipation which can be a critical factor for the microprocessors used in portable battery operated devices. Recently double gate Finfet has been reported to reduce leakage current effectively through it using threshold voltage control through back gate biasing technique. In this paper a new Finfet based wide fan-in dynamic OR gate has been proposed with reduced leakage and high noise immunity. This work reports a maximum leakage power reduction up to 70% while maintaining high noise immunity as compared to basic dynamic OR gate.

Register file structures in modern microprocessors usually employ wide fan-in dynamic CMOS OR gates. Weak keepers have been traditionally used to resolve the low noise margin problem of dynamic CMOS design. Scaling trends and process variation issues in CMOS design have reduced the effectiveness of this weak PMOS keeper. On the other hand large sized PMOS keeper used in wide fan-in dynamic OR gate results in contention between the pull down network (PDN) and the keeper. As a consequence of contention there is an unnecessary increase in power dissipation and loss in performance. In this paper a process variation tolerant wide fan-in dynamic OR gate with a new keeper design is proposed which is capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. Simulation results at 50 nm shows that the power dissipation and delay have been reduced by 40% and 35% respectively as compared to the wide fan-in dynamic OR gate with conventional keeper under different levels of process variation.

Register file structures in modern microprocessors usually employ wide fan-in dynamic CMOS OR gates. Weak keepers have been traditionally used to resolve the low noise margin problem of dynamic CMOS design. Scaling trends and process variation issues in CMOS design have reduced the effectiveness of this weak PMOS keeper. On the other hand large sized PMOS keeper used in wide fan-in dynamic OR gate results in contention between the pull down network (PDN) and the keeper. As a consequence of contention there is an unnecessary increase in power dissipation and loss in performance. In this paper a process variation tolerant wide fan-in dynamic OR gate with a new keeper design is proposed which is capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. Simulation results at 50nm shows that the power dissipation and delay have been reduced by 40% and 35% respectively as compared to the wide fan-in dynamic OR gate with conventional keeper under different levels of process variation.

With the scaling of technology the magnitude of leakage current has become a major cause of concern as it reduces the robustness of the circuit and leads to wastage of power. Most of the methods of leakage reduction lead to an increase in the delay of the circuit. In this paper a delay minimization block is proposed. This block is incorporated in a domino gate which has high threshold transistors for leakage reduction. The delay of high threshold domino gates has been reduced by using this mechanism. This facilitates the placement of high threshold domino gates in the critical or near critical paths of a design. Delay reduction of about 10% is achieved without any penalty on power delay productwhen wide fan-in domino gate has leakage as well as delay reduction features as compared to wide fan-in domino gates with only leakage reduction mechanisms. Simulations at 500MHz in 90nm show that leakage has reduced by 50% in the proposed design as compared to the conventional wide fan-in domino gate.

In this paper a new design technique is proposed using FTL (Feed through Logic) concept for high performance dynamic CMOS logic with high noise immunity and low power. FTL improves the performance of arithmetic circuits with a very long logic depth. In spite of its performance advantage, FTL suffers from reduced noise margin, direct path current and non-zero nominal low output voltage. The proposed technique removes the charge sharing problem and increases the noise immunity of high performance dynamic FTL circuit. In order to evaluate the efficacy of the proposed technique a high performance dynamic 2-input AND gate is designed and realized using the proposed technique. A comparative analysis of the proposed technique, Feed Through Logic and Domino Logic has been done in terms of noise immunity, power dissipation and delay. A comparative analysis is also carried out by simulating the above dynamic logic circuits in 180nm and 90nm technology with supply voltages of 1.8V and 1V respectively. At 180nm technology the Average Noise Threshold Energy (ANTE) & Energy normalized ANTE of proposed technique is improved by 4.35X & 1.65X over conventional Domino and 1.96X & 3.49X over conventional FTL. Power dissipation is reduced by 3.69X & 3.50X over conventional Domino and conventional FTL respectively.