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Always-on keyword spotting (KWS) hardware is gaining popularity in ultra-low power IoT applications where specific words are used to wake up and activate the power hungry downstream system. This work proposes a low power KWS engine with a power-optimized Mel-frequency cepstral coefficients (MFCC) feature extraction module and a memoryoptimized long short term memory (LSTM) accelerator. Our LSTM model is pruned and compressed to reduce 89% of model size and 76% of computation. The LSTM accelerator adopts the weight stationary dataflow to reduce energy. Our simulation using a 40nm CMOS process achieves a power consumption of 2.51 μW, which is at least 2× lower than the state-of-the-art.

In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved according to the sparse spiking and non-uniform traffic of SNN. In this paper, we propose a 5.28-mm² 4096-neuron 1M-synapse energy-efficient digital SNN hardware that can achieve ultra-low energy per synaptic operation of 4.5 pJ. The proposed neuron computing unit is implemented in pipeline architecture to achieve high synaptic processing speed. The proposed spike processing unit can significantly increase the processing speed of the neuron core by 1.9x and 9.4x when the spike injection rate is 50% and 10%, respectively. Besides, the increase in the processing speed of the neuron core leads to a reduction in energy consumption of up to 81.5%. An event-driven clock gating circuit that can reduce the power consumption of the proposed neuron block by more than 70% is proposed in this paper. This paper proposes a supervised STDP+ algorithm for SNN training, and the classification accuracy of the MNIST digits is 89.6% with 73.6% weight sparsity of the output layer.

This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves around a high- $V_{th}$ SRAM to reduce leakage, alongside reconfigurable neuron compute logic circuits and async routers to maximize energy efficiency. The neuron compute module achieves low power via an area efficient ALU implementation by using only adder and bitshifter circuits. We describe this LIF neuron model ALU design, and also include key neurocore verification scenarios (i.e., router deadlocks and functional coverage), CPU-neurocore control flow, and asynchronous router performance analysis. Our 16-core fabricated chip in 40 nm CMOS process works down to 0.5V. The measured leakage and average energy efficiency are $0.93~\mu \text{W}$ /core and 4.8 pJ/SOP respectively (at 0.5V), which is 20% better than state of the art.

Neuromorphic (NC) designs have gained significant interest in recent hardware research due to its low-power consumption. Low-power and low-latency router design is one of the most critical component to ensure NC hardware’s scalability and energy efficiency. Various router designs have been proposed to achieve high performance. However, this leads to complex router architectures and thus high area and power consumption. Furthermore, non-uniform traffic patterns of spiking neurons can cause network congestion and unnecessary power consumption. In this brief, we propose a congestion-aware routing algorithm to alleviate the congestion of routers in the middle and reduce network latency. Besides, a globally asynchronous, locally synchronous low-cost router architecture is deployed to relax the global clock tree constraint at chip level. Finally, a novel clock gating circuit is proposed to reduce the dynamic power consumption of routers. Our results show that averagely it reduces the router power consumption by more than 50%. The proposed router achieves ultra-low energy consumption of $2.3\times 10^{-2}$ pJ/bit and a small area of only 0.007 mm2.

Activation functions such as hyperbolic tangent (tanh) and logistic sigmoid (sigmoid) are critical computing elements in a long short term memory (LSTM) cell and network. These activation functions are non-linear, leading to challenges in their hardware implementations. Area-efficient and high performance hardware implementation of these activation functions thus becomes crucial to allow high throughput in a LSTM accelerator. In this work, we propose an approximation scheme which is suitable for both tanh and sigmoid functions. The proposed hardware for sigmoid function is 8.3 times smaller than the state-of-the-art, while for tanh function, it is the second smallest design. When applying the approximated tanh and sigmoid of 2% error in a LSTM cell computation, its final hidden state and cell state record errors of 3.1% and 5.8% respectively. When the same approximated functions are applied to a single layer LSTM network of 64 hidden nodes, the accuracy drops by 2.8% only. This proposed small yet accurate activation function hardware is promising to be used in Internet of Things (IoT) applications where accuracy can be traded off for ultra-low power consumption. Accepted version We thank the Programmatic grant no. A1687b0033, Singapore RIE 2020, AME domain.

High performance but computationally expensive Convolutional Neural Networks (CNNs) require both algorithmic and custom hardware improvement to reduce model size and to improve energy efficiency for edge computing applications. Recent CNN architectures employ depthwise separable convolution to reduce the total number of weights and MAC operations. However, depthwise separable convolution workload does not run efficiently in existing CNN accelerators. This paper proposes an energy-efficient CONV unit for pointwise and depthwise operation. The CONV unit utilizes weight stationary to enable high efficiency. The row partial sum reduction is engaged to increase parallelism in pointwise convolution thereby lightening the memory requirements on output partial sums. Our design achieves a maximum efficiency of 3.17 TOPS/W at 0.85V/40nm CMOS which is well-suited for energy constrained edge computing applications. Accepted version

The complexity and cost of system-on-chip (SoC) designs keep increasing every year, which has progressively led to more opportunities for 2.5D System-in-Package (SiP) design. While 2.5D integration technology offers advantages for heterogeneous chiplet-based systems, it also poses challenges of a more complex overall design flow with limited EDA tools support, physical design optimization issues, interposer floor-planning difficulties and complex system-level verification. Furthermore, accurate inter-chiplet connection modeling, chiplet characterization and top-level simulation activities are also needed for comprehensive verification of SiPs. To tackle these challenges, we share an automated chiplet-based codesign flow: built on the backbone with standard EDA design tools, an automatic SiP register transfer language (RTL) generator is developed for top-level SiP netlist generation; inter-chiplet connection routing with chip assembly router and parasitic extraction tools; interposer design and bumps placement with the foundry defined redistribution layer (RDL).

With the semiconductor industry moving towards smaller and more advanced process nodes, the reliability of the fabricated system-on-chips (SoCs) has become a significant problem, although it can be mitigated by proper verification and validation methodologies. Typical neuromorphic SoC chips are resource constrained and have very low power envelopes, pushing designers to forego the integration of onchip debug circuits. Futhermore, these specialized neuromorphic SoCs may not even be capable of supporting memory debug circuits due to the inclusion of novel memory types. Hence, it is a huge challenge to execute a comprehensive system level post-silicon validation suite on such chips, while aiding debugging efforts reliably. This paper presents a post-silicon validation methodology and algorithm to test all the neurocores within our custom designed neuromorphic processing unit (NPU) chip, focused on pinpointing the faults on the synaptic weight storage elements. The described methodology does not require any specialized built-in debug circuits to infer and detect faults. Based on the test results, the custom NPU chip was able to respond accordingly to all performed tests under optimal voltage and frequency conditions.

This paper proposes a scalable hardware architecture for block-based spiking neural networks utilizing a multiplierless spiking neuron model. These blocks were implemented as a neurocore mesh generated from an interconnect algorithm, allowing for seamless scalability of the network size while mitigating connectivity errors. The routing fabric asynchronous protocol allows for critical timing paths between blocks to be relaxed. The proposed neuron model consumed less logic compared to standard models with multipliers, reducing up to 16% of the neurocore logic cell area. The network was implemented alongside a computing subsystem as an FPGA-based system-on-chip, communicating via a fabric interconnect bridge. Experimental results validate the functionality of the proposed system, and achieved comparable classification accuracy to existing works.

Network-on-Chip has been widely used as an interconnection fabric due to its high scalability. However, traditional router designs target multiprocessor systems-on-chips, and therefore needs to be improved according to the characteristics of neuromorphic computing. This paper proposes an ultra low power and low area router for neuromorphic computing. Clock gating technique is used to reduce router power consumption by reducing clock activities. The proposed router uses small FIFO based interface links to reduce router area. A modified round robin arbiter is proposed to reduce the router latency. The wormhole model is improved to make it better match neuromorphic computing applications. An ultra low power and small size ring oscillator was designed to provide a global clock to all design blocks. Experimental results show that the average power consumption of the proposed router is 0.26mW, and only 0.01mW when idle. It occupies a much smaller area (0.007 mm 2) compared to other router designs described in previous works. It can be seen from the experimental results that after the clock gating circuitry is added, the total power consumption of $a3 \times3$ router array is significantly reduced, approximately $2.1 \times$ lower when busy and $21 \times$ lower when idle.

The possibility of encapsulation of one and two H 2 molecule inside C 50 fullerene was investigated at MP2 level of theory. By calculating the complexation energy, it was confirmed that H 2 @C 50 complex is thermodynamically stable, while 2H 2 @C 50 one is unstable. This was evidenced by negative complexation energy for H 2 @C 50 and positive one for 2H 2 @C 50 calculated using different basis sets. Examination of the host–guest interaction forces and strain energies in both complexes and the maximum expansion of the C 50 cage before C–C bonds breaking also proved that only one H 2 can reside inside the C 50 cage.

Heart arrhythmia is a fairly common medical condition, in which abnormal electrical activity occurs in the heart. However, it can be life threatening if left untreated or undiagnosed. This paper introduces an improved method to classify heart arrhythmia from electrocardiogram (ECG) signals using Block-based Neural Networks (BbNN). BbNNs are used in the hardware implementation of this problem due to its regular block based structure, relatively fast computational speeds, and lower resource consumption. The training mechanism for evolving BbNNs used in the work utilizes Genetic Algorithm (GA), but is able to handle larger sets of training data more efficiently due to an implementation of a novel multithreaded fitness evaluation approach. The ECG heartbeat dataset is taken from the MIT-BIH arrhythmia database, and feature extraction is done using the evaluation of Hermite polynomials on the preprocessed ECG signal. The proposed BbNN system-on-chip (SoC) shows high accuracy in its arrhythmia classification, with an average accuracy of 99.64% for all tested patient records.

The flyback switching mode power supply (SMPS) circuit is undoubtedly the most popular topology currently in low power applications, due to its low cost and simple structure. In the past, there have been many proposed optimizations to flyback designs utilising various techniques such as zero voltage switching (ZVS), active clamping, synchronous rectification, and more. However, most of these designs complicate the original snubbed structure of the flyback topology, and increases its cost. This paper presents the evaluation of a variable-frequency, soft-switching, snubbed, DC/DC flyback converter that utilizes valley switching for improving efficiency. The flyback controller is modelled using SPICE, and uses pulse skipping to maintain the equilibrium of the system based on the feedback from the output. Simulation models report up to 92.2% efficiency, which is almost comparable to ZVS and active clamping topologies. The main advantage of this design is the use of only a single switching transistor, with no additional inductors, correctional circuitry, or clamping action, thus guaranteeing a low cost design.

Studies have shown that driver drowsiness is one of the main causes of road accidents. It is estimated that 30% of road accidents are caused by driver drowsiness, which creates a need for driver drowsiness detection in modern vehicle systems. Previous works have shown the viability of using heart rate variability (HRV) for detecting the onset of driver drowsiness. HRV is obtained for electrocardiogram (ECG) signals, of which the power bands can be analysed to determine the physiological state of a person. This paper introduces a new method to detect driver drowsiness by classifying the power spectrum of a person's HRV data using Block-based Neural Networks (BbNN), which is evolved using Genetic Algorithm (GA). For most cases, regular Artificial Neural Networks (ANN) are not suitable for high speed and efficient hardware implementation. BbNNs are better candidates due to its regular block based structure, has relatively fast computational speeds, lower resource consumption, and equal classifying strength in comparison to other ANNs. Preliminary work has shown promising results with up to 99.99% classification accuracy using the proposed BbNN detection system for HRV data.

As concerns about security in networking and communication systems rise with their rapid technology advancements, the need for more reliable and stronger user authentication techniques has also increased. Traditional security methods such as personal identification number, password, and key smart cards are proving to be more and more inadequate, especially in large-scale authentication systems. Hence today, the biometric-based security system is gaining acceptance as an effective tool for providing information security, as can be seen by its deployment in various commercial, public, border control and governmental applications. Each biometric technique has its own merits, but recently, finger-vein biometrics has shown great promise with some key advantages over the other biometrics, which include fingerprint, face, iris and voice. Research has shown that finger-vein biometrics yield very low error equal rates (EER). However, there is more room for improvement. This paper presents a method to optimize finger-vein detection by using genetic algorithms (GA) to fine-tune the image processing parameters in an finger-vein biometric FPGA-based system-on-chip embedded system. The parameters that are tunable include threshold levels and filtering parameters. Experimental results show that the optimization process can successfully reduce the EER from 1.004% to 0.101% on the same biometric system, negating the need for an expert system designer intuition on the image processing parameters.

The Transport Layer Security (TLS) protocol is currently the predominant method of implementing Internet security. This paper proposes an FPGA-based embedded system integrating hardware that accelerates the cryptographic algorithms used in the SSL/TLS protocol. OpenSSL, an open source implementation of the SLL v3 and TLS v1 protocol, is deployed in the proposed embedded system powered with a Nios-2 embedded soft-core processor. Nios2-Linux RTOS is applied, which serves to provide Ethernet connectivity, multitasking, and support for the OpenSSL library. Key cipher functions used in SSL-driven connections, which include AES-256 symmetric encryption, SHA-2 hashing, RSA-2048 publickey cryptography, are accelerated in hardware. The embedded cryptosystem is prototyped completely on an Altera Stratix II FPGA development board. Experimental results show significant improvements in performance of the SSL transactions when the proposed embedded cryptosystem is deployed in the networking system.

This paper presents the implementation of a tightly coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate Advanced Encryption Standard (AES) operations in 128, 192 and 256-bits, for application in a high-performance embedded system implementing symmetric key cryptography. The concept is to augment the embedded processor with a new custom instruction for encryption and decryption operations. In order to show the effectiveness of tightly coupled hardware implementation over coprocessor based approach, we have also realized the design in coprocessor approach using the same AES core. Experimental results show that for the encryption or decryption operations, real implementation with custom instructions and tightly coupled hardware is about 35% faster than the co-processor based hardware.

The internet is an insecure medium and hence, there is an increasing demand for measures to guarantee data privacy and integrity in the associated computer systems and networks. However, data protection and network security comes at a very high cost in the supporting embedded systems. While there are freely available solutions such as the OpenSSL library, the performance of most embedded processors, on their own, are just not adequate enough to perform cryptography for real-time network security applications. In this paper, we focus on the implementation of a cryptographic (crypto) embedded system, deploying an Altera Nios II embedded processor working with an AES encryption hardware accelerator. The RTOS applied is uClinux, on which the OpenSSL library has been ported and cross-compiled. Experimental results show that hardware acceleration can improve, significantly, the performance of OpenSSL crypto functions and hence, of the SSL connection as well.