281 results on '"Volkan Kursun"'
Search Results
2. Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor Technology.
3. Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater.
4. Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections.
5. Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers.
6. Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density.
7. Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters.
8. Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
9. Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors.
10. Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode.
11. Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes.
12. Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic.
13. Carbon-based sleep switch dynamic logic circuits with variable strength keeper for lower-leakage currents and higher-speed.
14. 2-Phase high-frequency clock distribution with SPLIT-IO dual-Vt repeaters for suppressed leakage currents.
15. Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability.
16. Low power and robust memory circuits with asymmetrical ground gating.
17. Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode.
18. High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins.
19. A comprehensive comparison of superior triple-threshold-voltage 7-transistor, 8-transistor, and 9-transistor SRAM cells.
20. Triple-threshold-voltage 9-transistor SRAM cell for data stability and energy-efficiency at ultra-low power supply voltages.
21. Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins.
22. 5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets
23. A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors.
24. Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption.
25. Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits.
26. Novel dual-threshold-voltage energy-efficient buffers for driving large extrinsic load capacitance.
27. Low-power and compact NP dynamic CMOS adder with 16nm carbon nanotube transistors.
28. Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability.
29. Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins.
30. Ground gated 8T SRAM cells with enhanced read and hold data stability.
31. Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cells.
32. A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability.
33. Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits.
34. NP dynamic CMOS resurrection with carbon nanotube field effect transistors.
35. Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations.
36. Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETs.
37. Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical quality.
38. Leakage current and bottom gate voltage considerations in developing maximum performance 16nm N-channel carbon nanotube transistors.
39. Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits.
40. Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits.
41. Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits.
42. Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops.
43. Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs.
44. Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits.
45. A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations.
46. Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits.
47. Low power and robust 7T dual-Vt SRAM circuit.
48. Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.
49. Dynamic wordline voltage swing for low leakage and stable static memory banks.
50. Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.