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1. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

Author

J. Verluijs, V. Truffert, Geert Vandenberghe, J. De Backer, Marc Demand, E. Altamirano, M. Ercken, G. Mannaert, Christina Baerts, Anne Lauwers, Stephan Brus, T. Hoffman, S. Locorotondo, T. Vandeweyer, Andriy Hikavyy, W. Alaerts, Gerald Beyer, J. Hermans, Herbert Struyf, Serge Biesemans, Craig Huffman, Michal Rakowski, Nancy Heylen, C. Delvaux, Frederic Lazzarino, S. Verhaegen, Steven Demuynck, Henny Volders, Patrick Ong, Christa Vrancken, H. Dekkers, Philippe Absil, Kurt G. Ronse, Naoto Horiguchi, and Kristof Kellens

Subjects
Materials science, business.industry, Extreme ultraviolet lithography, Logic gate, MOSFET, Multiple patterning, Optoelectronics, Nanotechnology, business, Metal gate, Lithography, Integrated circuit layout, High-κ dielectric
Abstract

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

Published
2010
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