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Fully-processed SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) emit light during switching of the gate terminal, while both drain and source terminals are grounded. The emitted photons are caused by defect-assisted recombination of electrons and holes at the 4H-SiC/SiO$_2$ interface and can be detected through the SiC substrate. Here, we present time-gated spectroscopic characterization of these interfacial point defects. Unlike in previous studies, the devices were opened in such a way that the drain-contact remained electrically active. A separate examination of the photons emitted at the rising and falling transitions of the gate-source voltage enabled the extraction of two different spectral components. One of these components consists of a single transition with phonon replicas of a local vibrational mode (LVM) with an astonishingly high energy of 220 meV $\unicode{x2013}$ well above the highest phonon modes in 4H-SiC and SiO$_2$ of 120 meV and 137 meV, respectively. Based on a quantum mechanical model, we successfully fitted its emission spectrum and assigned it to donor-acceptor pair recombination involving a carbon cluster-like defect. Other transitions were assigned to EH$_{6/7}$-assisted, EK$_2$-D, and nitrogen-aluminum donor-acceptor pair recombination. Due to the relevance of these defects in the operation of SiC MOSFETs, these novel insights will contribute to improved reliability and performance of these devices., Comment: 18 pages, 12 figures

Graphene is a promising material for applications as a channel in graphene field-effect transistors (GFETs) which may be used as a building block for optoelectronics, high-frequency devices and sensors. However, these devices require gate insulators which ideally should form atomically flat interfaces with graphene and at the same time contain small densities of traps to maintain high device stability. Previously used amorphous oxides, such as SiO2 and Al2O3, however, typically suffer from oxide dangling bonds at the interface, high surface roughness and numerous border oxide traps. In order to address these challenges, here we use for the first time 2nm thick epitaxial CaF2 as a gate insulator in GFETs. By analyzing device-to-device variability for over 200 devices fabricated in two batches, we find that tens of them show similar gate transfer characteristics. Our statistical analysis of the hysteresis up to 175C has revealed that while an ambient-sensitive counterclockwise hysteresis can be present in some devices, the dominant mechanism is thermally activated charge trapping by border defects in CaF2 which results in the conventional clockwise hysteresis. We demonstrate that both the hysteresis and bias-temperature instabilities in our GFETs with CaF2 are comparable to similar devices with SiO2 and Al2O3. In particular, we achieve a small hysteresis below 0.01 V for equivalent oxide thickness (EOT) of about 1 nm at the electric fields up to 15 MV/cm and sweep times in the kilosecond range. Thus, our results demonstrate that crystalline CaF2 is a promising insulator for highly-stable GFETs.

Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT). In this work we present Comphy v3.0, an open source physical framework for modeling these effects in a unified fashion using nonradiative multiphonon theory on a one-dimensional device geometry. Here we give an overview about the underlying theory, discuss newly introduced features compared to the original Comphy framework and also review recent advances in reliability physics enabled by these new features. The usefulness of Comphy v3.0 for the reliability community is highlighted by several practical examples including automatic extraction of defect distributions, modeling of TAT in high-k capacitors and BTI/RTN modeling at cryogenic temperatures.

Despite the enormous progress achieved during the past decade, nanoelectronic devices based on two-dimensional (2D) semiconductors still suffer from a limited electrical stability. This limited stability has been shown to result from the interaction of charge carriers originating from the 2D semiconductors with defects in the surrounding insulating materials. The resulting dynamically trapped charges are particularly relevant in field effect transistors (FETs) and can lead to a large hysteresis, which endangers stable circuit operation. Based on the notion that charge trapping is highly sensitive to the energetic alignment of the channel Fermi-level with the defect band in the insulator, we propose to optimize device stability by deliberately tuning the channel Fermi-level. Our approach aims to minimize the amount of electrically active border traps without modifying the total number of traps in the insulator. We demonstrate the applicability of this idea by using two differently doped graphene layers in otherwise identical FETs with Al$_2$O$_3$ as a gate oxide mounted on a flexible substrate. Our results clearly show that by increasing the distance of the Fermi-level to the defect band, the hysteresis is significantly reduced. Furthermore, since long-term reliability is also very sensitive to trapped charges, a corresponding improvement in reliability is both expected theoretically and demonstrated experimentally. Our study paves the way for the construction of more stable and reliable 2D FETs in which the channel material is carefully chosen and tuned to maximize the energetic distance between charge carriers in the channel and the defect bands in the insulator employed., Comment: 28 pages, 6 figures

Complementary metal oxide semiconductor (CMOS) logic circuits at the ultimate scaling limit place the utmost demands on the properties of all materials involved. The requirements for semiconductors are well explored and could possibly be satisfied by a number of layered two-dimensional (2D) materials, like for example transition-metal dichalcogenides or black phosphorus. The requirements for the gate insulator are arguably even more challenging and difficult to meet. In particular the combination of insulator to semiconductor which forms the central element of the metal oxide semiconductor field effect transistor (MOSFET) has to be of superior quality in order to build competitive devices. At the moment, hexagonal boron nitride (hBN) is the most common two-dimensional insulator and widely considered to be the most promising gate insulator in nanoscaled 2D material-based transistors. Here, we critically assess the material parameters of hBN and conclude that while its properties render hBN an ideal candidate for many applications in 2D nanoelectronics, hBN is most likely not suitable as a gate insulator for ultrascaled CMOS devices., Comment: 10 pages, 4 figures

Two-dimensional (2D) semiconductors have been suggested both for ultimately-scaled field-effect transistors (FETs) and More-than-Moore nanoelectronics. However, these targets can not be reached without accompanying gate insulators which are scalable into the nanometer regime. Despite the considerable progress in the search for channel materials with high mobilities and decent bandgaps, finding high-quality insulators compatible with 2D technologies has remained a challenge. Typically used oxides (e.g. SiO2, Al2O3 and HfO2) are amorphous when scaled, while two-dimensional hBN exhibits excessive gate leakages. To overcome this bottleneck, we extend the natural stacking properties of 2D heterostructures to epitaxial fluorite (CaF2), which forms a quasi van der Waals interface with 2D semiconductors. We report scalable single-layer MoS2 FETs with a crystalline CaF2 insulator of about 2 nm thickness, which corresponds to an equivalent oxide thickness of less than 1 nm. While meeting the stringent requirements of low leakage currents, our devices exhibit highly competitive performance and record-small hysteresis. As such, our results present a breakthrough for very large scale integration towards commercially competitive nano-electronic devices., Comment: The final publisher of this manuscript does not bare any responsibility for possible errors in this document

After nearly half a century of research into the bias temperature instability (BTI), two classes of models have emerged as the strongest contenders: one class of models, the reaction-diffusion models, is built around the idea that hydrogen is released from the interface and that it is the diffusion of some form of hydrogen that controls both degradation and recovery. While many different variants of the reaction-diffusion idea have been published over the years, the most commonly used recent models are based on non-dispersive reaction rates and non- dispersive diffusion. The other class of models is based on the idea that degradation is controlled by first-order reactions with widely distributed (dispersive) reaction rates. We demonstrate that these two classes give fundamentally different predictions for the stochastic degradation and recovery of nanoscale devices, therefore providing the ultimate modeling benchmark. Using de- tailed experimental time-dependent defect spectroscopy (TDDS) data obtained on such nanoscale devices, we investigate the compatibility of these models with experiment. Our results show that the diffusion of hydrogen (or any other species) is unlikely to be the limiting aspect that determines degradation. On the other hand, the data are fully consistent with reaction-limited models. We finally argue that only the correct understanding of the physical mechanisms leading to the significant device-to-device variation observed in the degradation in nanoscale devices will enable accurate reliability projections and device optimization.