528 results on '"Wambacq, Piet"'
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2. Introduction
3. A Background-Calibrated Digital Subsampling Polar Transmitter
4. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation
5. A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis
6. Summary and Conclusions
7. Design Considerations for High-Datarate Low-Power 60 GHz TX Front-Ends
8. Digitally-Modulated Polar Transmitters in 40 nm CMOS
9. 60 GHz TX Front-Ends in Advanced CMOS Technologies with Improved Back-Off Efficiencies
10. Introduction
11. Challenges of Digitally Modulated Transmitter Implementation at Millimeter Waves
12. A 33 dBm, >30% PAE GaN Power Amplifier Based on a Sub-Quarter-Wavelength Balun for 5G Applications
13. A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs
14. Resistive Charge-Based Transmitter
15. Capacitive Charge-Based Transmitter
16. Introduction
17. Incremental-Charge-Based Operation
18. Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout
19. Conclusion
20. Layout and Post-layout Simulations
21. Introduction
22. Background
23. Top-Level Design
24. Design and Simulation Results
25. RF linearity trade-offs for varying T-gate geometries of GaN HEMTs on Si
26. Introduction
27. Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission
28. Digitally-Modulated Polar Transmitters in 40 nm CMOS
29. 60 GHz TX Front-Ends in Advanced CMOS Technologies with Improved Back-Off Efficiencies
30. Summary and Conclusions
31. Design Considerations for High-Datarate Low-Power 60 GHz TX Front-Ends
32. Low-Power Millimeter Wave Transmitters for High Data Rate Applications
33. Conclusions
34. The Promise of 2-D Materials for Scaled Digital and Analog Applications
35. Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design
36. 4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL
37. Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS
38. Substrate Noise Coupling from Digital to Analog Circuits in Mixed-Signal Integrated Circuits
39. A 120–140-GHz LNA in 250-nm InP HBT
40. Theoretical Angular Resolution of Forward-Looking MIMO-SAR Systems
41. A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout
42. A 39-GHz 18.5-mW LNA with T/R switch, 15.4-dB gain, -2.2dBm IIP3, 5.6-dB NF, for a 5G in-cabin basestation in 22-nm FD-SOI
43. Fast: An Efficient High-Level Dataflow Simulator of Mixed-Signal Front-Ends of Digital Telecom Transceivers
44. Motivation, Context and Objectives
45. A 130GHz Two-Stage Common-Base Power Amplifier in 250nm InP
46. A Stacked Segmented Adaptive Power Amplifier in 22nm FD-SOI
47. A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS
48. A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS
49. Design and Analysis of 55–63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS
50. A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
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