532 results on '"Wang, Chua-Chin"'
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2. A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD
3. A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic
4. A single-chip PFM-controlled LED driver with 0.5% illuminance variation
5. A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder
6. A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process
7. A 92.95%-efficiency high-voltage dual-mode buck converter using 0.5-µm HV CMOS process.
8. A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process.
9. Underwater Image Enhancement Based on Light Field-Guided Rendering Network.
10. An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-[formula omitted] HV CMOS
11. A metastable RNG using interleaved NAND- and NOR-based TEROs
12. A 15.13 Mw 3.2 Ghz 8-Bit Carry Look-Ahead Adder Using Single- Phase All-N-Transistor Logic
13. A Single-Chip Pfm-Controlled Led Driver with 0.5% Illuminance Variation
14. A 1-6.5 Gbps Dual-Loop Cdr Design with Coarse-Fine Tuning Vco and Modified Dqfd
15. Accurate RR-Interval Detection with Daubechies Filtering and Adaptive Thresholding
16. Multifunctional In-Memory Computation Architecture Using Single-Ended Disturb-Free 6T SRAM
17. 0.7 % error rate 3A bidirectional current sensor using high voltage CMOS process
18. 2×VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process
19. A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process
20. A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process
21. A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process
22. Power-effective ROM-less DDFS Design Approach with High SFDR Performance
23. A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder
24. A 92.95%-efficiency high-voltage dual-mode buck converter using 0.5-µm HV CMOS process
25. Three-level DC-DC Buck Converter Architecture Using Digital Pulse Width Modulation
26. A negative voltage generator with 4-stage configurable parallel switching for smart window film applications
27. Accurate RR-Interval Detection with Daubechies Filtering and Adaptive Thresholding
28. Multifunctional In-Memory Computation Architecture Using Single-Ended Disturb-Free 6T SRAM
29. 500 MHz 90 nm CMOS 2 × VDD Digital Output Buffer Immunity to Process and Voltage Variations
30. A 90-nm CMOS 800 MHz 2×VDD output buffer with leakage detection and output current self-adjustment
31. 56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology
32. A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM
33. Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle
34. A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process
35. A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array
36. A 19.38 dBm OIP3 gm-boosted up-conversion CMOS mixer for 5–6 GHz application
37. A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems.
38. A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process.
39. Single-chip DC–DC buck converter design based on PWM with high-efficiency in light load.
40. A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits
41. A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process
42. A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition
43. A 30 V rail-to-rail operational amplifier
44. Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring
45. A ±3.07% frequency variation clock generator implemented using HV CMOS process
46. Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology
47. A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology
48. A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture
49. A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module
50. A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder
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