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With the development of high-temperature packaging technology, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (mosfets) can operate under high-temperature conditions with junction temperatures exceeding 175 °C, providing a solution for pulsed power applications facing instantaneous high currents and significant temperature fluctuations. However, the electro-thermal coupling behaviors and safe operating area (SOA) of SiC mosfets in a wide temperature range are unclear, and there is a lack of guiding principles for SiC module packaging and heat dissipation design in pulsed power applications. In this article, an electro-thermal coupling model of SiC mosfet modules is established. The electrical model over a wide temperature range (25 °C–375 °C) is built in Simulink, and the thermal finite element model is established in COMSOL, while MATLAB script is used to implement interaction between the two models. Then, detailed analyses are conducted on the electro-thermal coupling behaviors of SiC mosfet modules. Besides, the impact of packaging on the SOA of SiC mosfet modules is researched. In addition, a transient junction temperature measurement method of SiC mosfets is proposed by using the on-state resistance Rds(on) as the temperature-sensitive electrical parameter. Finally, the discharge experiments of the capacitor bank through resistive loads are carried out under short pulse and long pulse, respectively, and the experimental results are consistent with the model.

Press-pack power module has recently become a crucial component for large-current and high-power facilities. Several semiconductor chips are connected in parallel inside the module. Due to the complex coupling of electrical, thermal, and mechanical fields within the device, the imbalance in pressure distribution and heat dissipation capacity may lead to uneven current distribution and potential overloading of certain chips. Chip-level online current sensing is an effective approach to provide current monitoring and fault diagnosis. However, it is difficult to accomplish high-accuracy chip-level current sensing considering the bandwidth and size of sensors. In this article, a compact hybrid sensor consisting of anisotropic magnetoresistance (AMR) and Rogowski coil for chip-level online sensing is proposed. Rogowski coil possesses the advantage to measure the high-frequency current and AMR sensor is used to expand the dc and low-frequency bandwidth of the coil. The principle and the design of Rogowski coil and AMR sensor are analyzed. The magnetic fields generated by multiple chips tend to couple with each other. To enhance the accuracy of AMR, a decoupling matrix is calculated to decouple the crosstalk of magnetic fields. The implementation of the hybrid sensor is proposed. The hybrid sensor is used to measure the chip-level current of a press-pack insulate gate bipolar transistorv (IGBT) in a buck converter whose frequency is 40 kHz. The output of hybrid sensor is verified by the commercial current transducer. The result shows that the hybrid sensor achieves chip-level current sensing for press-pack power module, with a measurement bandwidth ranging from dc to 30 MHz, an accuracy of 2% and excellent linearity.

All silicon carbide (SiC) devices have the advantages of high switching speed and low loss. The current slew rate di/dt, current and voltage spikes, oscillation current/voltage, and turn-on loss (DOSs) are important electrical indicators for power devices during the switching process. However, there are few analytical expressions that balance accuracy and simplicity for quantitative analysis of DOSs due to nonlinear issues. This article derives the linearized analytical expressions for DOSs and analyzes the sensitivity of current and voltage spikes to different parameters during the turn-on process based on a piecewise linearization method. The analytical expressions provide an intuitive description of the relationship between DOSs and different parameters. For example, the phenomenon where voltage spikes of the high-side device do not monotonically decrease with the increase of driving resistance is discovered and explained. The sensitivity offers guidance for accurate and simplified linear processes in DOS calculations. The simplified equivalent output capacitance method and accurate dynamic current slew rate are proposed in the linearization process, as the current and voltage spikes have low sensitivity to output capacitance and high sensitivity to the current slew rate. The piecewise linearization method for calculating DOSs is verified by double pulse test (DPT) experiments and the relatively optimal driving resistance is designed and discussed.

To expand current rating and facilitate the use of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) in high-power applications, multichip GaN power modules with paralleled GaN HEMTs are urgently needed. Existing GaN packages mainly focus on lowering inductances and thermal resistances, rarely involving current sharing. For multichip GaN modules, the package also requires more flexible layouts to achieve symmetrical layouts for current sharing, which is more challenging. In this article, we propose a novel hybrid double-side cooled (DSC) package, where a flexible printed circuit board (PCB) is heterogeneously integrated to expand the layout flexibility and GaN HEMTs can be cooled on both sides. The flexible layout allows the entangled power and gate layouts of paralleled GaN HEMTs to be separated and optimally laid out. Based on this package, decoupled switching cells and integrated gate drivers are implemented in the multichip GaN module, enabling consistent layouts and low inductances. Also, the scaling of current ratings can be easily realized. The electromagnetic coupling, thermal performance, and reliability are also analyzed in detail. By experiments, the multichip GaN hybrid DSC module has good insulation properties and ensures current sharing at switching speeds up to −29.3 A/ns and 204 V/ns. In addition, the thermal verification and applied weight experiment are also carried out.

The safe operation and lifetime of the power module are heavily dependent on the temperature distribution, making it imperative to optimize the thermal performance of the layout at the design stage. During the module design phase, a significant number of layouts are assessed. It is important to constrain computational complexity while achieving high accuracy. Mechanistic modeling and data-driven modeling have limitations in terms of complexity and generalizability respectively. Therefore, this article proposes a hybrid data-driven and mechanistic modeling approach. This approach incorporates the theoretical analysis of mechanistic modeling and the high efficiency of data-driven modeling to accurately and efficiently compute the temperature distribution of a given layout. This approach initially acquires the dataset from simple structures and conducts a dimensionality reduction to obtain the isothermal point set (IPS). Later, IPS of complex structures is developed based on mechanistic modeling. Finally, the IPS is converted to a field to obtain a temperature distribution of the given layout. The accuracy of the approach is verified by a steady-state thermal experiment. With the proposed approach, an accurate assessment of surface thermal distribution of different layouts can be quickly finished. The thermal characteristics evaluation efficiency can be improved roughly 300 times, which provides the necessary technical basis for layout optimization.

In a wireless power transfer (WPT) system, the coil-to-coil transfer efficiency is significantly influenced by the performance of coupling coils. The self-resonant coil is widely employed for its excellent performance. Existing coil modeling methods suffer from significant errors or computational complexity, making them unsuitable for the design and optimization of coils. This article presents a modified analytical method for self-resonant coil modeling, with a specific focus on calculating the self-resonant frequency (SRF), ohmic resistance, and quality factor. First, considering the nonidentical current distribution along the self-resonant coil, a segmented filament model is formulated to calculate the SRF and current distribution. Furthermore, the uneven current density distribution on the wire's cross section is considered, and a modified segmented filament model is presented, where the current density is equated to a conduction current filament plus a pair of proximity current dipoles. The magnetic field arising from neighboring wires can, then, be calculated, enabling the determination of ohmic resistance and quality factor. Simulation and measurement results validate the accuracy of the modified model for both tightly and loosely wound coils. This model is employed to optimize the ohmic resistance and quality factor during the coil design process. To further enhance the quality factor across the entire operating frequency range, an unequal-pitch coil structure is proposed, along with a novel design guideline for coil optimization. Following this guideline, a 6.71 MHz unequal-pitch self-resonant coil is designed, fabricated, and measured. The coil-to-coil transfer efficiency reaches 95.8% and 82.7% at a transfer distance-to-coil diameter ratio of 1 (${{d}_{\text{TR}}} = 20{\rm{\ cm}}$) and 2 (${{d}_{\text{TR}}} = 40{\rm{\ cm}}$), respectively. Furthermore, an experimental prototype of a high-efficiency mid-range WPT system is constructed using the optimized coils. Specifically, the overall efficiency of the WPT system reaches 81.2% when ${{d}_{\text{TR}}} = 20{\rm{\ cm}}$ and 63.2% when ${{d}_{\text{TR}}} = 40{\rm{\ cm}}$.