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Hospital readmission prediction is a study to learn models from historical medical data to predict probability of a patient returning to hospital in a certain period, 30 or 90 days, after the discharge. The motivation is to help health providers deliver better treatment and post-discharge strategies, lower the hospital readmission rate, and eventually reduce the medical costs. Due to inherent complexity of diseases and healthcare ecosystems, modeling hospital readmission is facing many challenges. By now, a variety of methods have been developed, but existing literature fails to deliver a complete picture to answer some fundamental questions, such as what are the main challenges and solutions in modeling hospital readmission; what are typical features/models used for readmission prediction; how to achieve meaningful and transparent predictions for decision making; and what are possible conflicts when deploying predictive approaches for real-world usages. In this paper, we systematically review computational models for hospital readmission prediction, and propose a taxonomy of challenges featuring four main categories: (1) data variety and complexity; (2) data imbalance, locality and privacy; (3) model interpretability; and (4) model implementation. The review summarizes methods in each category, and highlights technical solutions proposed to address the challenges. In addition, a review of datasets and resources available for hospital readmission modeling also provides firsthand materials to support researchers and practitioners to design new approaches for effective and efficient hospital readmission prediction.

The data compression technology now is fully developed and widely used in many fields such as communication, multi-media, image information processing and so on. The large physical experiments, especially the ones with Micro-pattern Gas Detectors (MPGD), which always have many readout channels and have a lot of data to be transferred and saved, are however relatively seldom use this technology. In this paper, the real-time lossless data compression method is proposed for a general-purposed MPGD readout system. The lossless data compression can reduce the data transmission bandwidth of the system as well as keep all information of the data. The compression method discussed in the paper mainly consists of two steps. The first step is to pre-process the data according to different characteristics of different signals and the second step is to compress the pre-processed data using common lossless compression algorithm. Besides, the whole compression method is implemented in the Field-Programmable Gate Array (FPGA) and able to run real-timely. The system is then used to readout two different kinds of signals and the compression rate can reach as high as 43% and 30% respectively.

At the China Jinping Underground Laboratory, the Particle AND Astrophysical Xenon phase IV (PandaX-4ton) in planning is a dark matter direct detection experiment with dual-phase xenon detector as an upgrade of the second phase of the experiment, PandaX-II. In this paper, the prototype of the front-end electronics of PandaX-4ton is presented. The front-end electronics consist of the high-gain preamplifier cards and the eight-channel digitizers with 14-bit resolution and 1 GSps sampling rate for waveform digitization. The clock synchronization circuit within the digitizer is well-designed to align all the PMT channels. The digitizer also contains gigabit fiber to exchange data with trigger and data acquisition system. The specification of effective number of bits f the digitizer is about 9.7 b at 148 MHz, and the integral nonlinearity of the digitizer ranges from -4 least significant bit (LSB) to +4 LSB, and the differential nonlinearity ranges from -0.6 LSB to +0.6 LSB. The performance of the front-end electronics can meet the requirements for the PandaX-4ton.

In recent years, high speed and high resolution analog-to-digital converter (ADC) is widely employed in many physical experiments, especially in high precision time and charge measurement. The rapid increasing amount of digitized data demands faster computing. FPGA acceleration has an attracting prospect in data process for its stream process and parallel process feature. In this paper, an ADC performance calibration application based on FPGA acceleration is described. FPGA reads the ADC digitized data stream from PC memory, processes and then writes processed result back to the PC memory. PCIE bus is applied to increase the data transfer speed, and floating point algorithm is applied to improve the accuracy. The test result shows that FPGA acceleration can reduce the processing time of the ADC performance calibration compared with traditional method of C-based CPU processing. This frame of PCIE-based FPGA acceleration method can be applied in analysis and simulation in the future physical experiment for large ADC array, such as CCD camera and waveform digitization readout electronics calibration., Comment: 2 pages, 4 figures, 21st IEEE Real Time Conference