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Quantum computers are expected to one day be able to solve a set of problems which are practically impossible with classical super computers, even with their projected continued improvement. As the field of quantum computing has continued to evolve the somewhat disparate research areas of algorithms and hardware have improved in their integration. Fully optimizing quantum algorithms requires a solid understanding of the quantum hardware, and metering experimental hardware priorities requires an understanding of the general algorithm requirements. This thesis initially provides an overview of quantum hardware and applications and discusses their interplay in both the near term and fault tolerant regime. A greater focus is placed on trapped ion architectures in this thesis and in particular the shuttling based approach of the Ion Quantum Technology group at the University of Sussex. A routing algorithm is provided which can efficiently enable all to all connectivity for the shuttling based trapped ion design without positional swaps. A simulation tool was created and used to develop and characterize routing algorithms. The cost of enabling connectivity in Noisy-Intermediate-Scale-Quantum devices is an important factor in determining computational power. The core ideas of this routing algorithm are currently being integrated into a software compiler stack that will control real quantum hardware. An error model for the shuttling based design is presented which makes use of the time cost for connectivity results from the simulation tool. The error model is used to estimate the computational power (quantum volume) of the design as a function of experimental parameters. The error model can be used to help meter experimental priorities by identifying the most impactful parameters across particular regimes. A comparison is performed using metrics such as Quantum Volume, between the shuttling based trapped ion design and a superconducting grid which uses logical swaps to enable connectivity, and it is found that the trapped ion design has a substantially lower cost associated with connectivity. Large scale trapped ion devices are considered and the total time required to enable all to all connectivity is estimated for both the modular shuttling approach and for the approach that uses small scale modules connected via photonic interconnects. A review of fault tolerant methods for quantum chemistry is presented. Resource estimations are provided all the way down to the required wall-clock time and number of physical qubits, for ground state energy calculations for molecules across different basis set sizes. The basis set size at which a quantum computer can meaningfully outperform a classical supercomputer is estimated. Determining the point at which a quantum advantage may be realised can help the field progress by setting realistic expectations and by having a device size to aim for. The impact of hardware considerations such as the code cycle time is investigated by including a wider range of possible surface code error correction configurations. Two distinct methods are investigated which allow one to incrementally speed up the rate of computation until the time optimal limit is reached by introducing additional qubits. The number of physical qubits required to reach a desirable run time is estimated as a function of the hardware's code cycle time, for problems such as the ground state estimation of the FeMoco molecule, and for breaking the encryption of the Bitcoin network. It is found that for the quantum advantage problems investigated in this work, hardware with considerably slower code cycle times than the more usually considered 1µs of superconducting qubits, will still be able to reach desirable run times provided enough physical qubits are available.