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Stress from edge dislocations introduced by solid phase epitaxial regrowth increases as gate pitch is scaled, reaching 1GPa at 100nm gate pitch. This scaling trend makes edge dislocations attractive for future technology nodes, as stress from epitaxial and deposited film stressors reduces as pitch is scaled (1,2). We show a gate last flow is best for maximizing the dislocation stress, and the stress varies with layout and topography. We arrive at these results by the application of the finite element method to model the dislocation stress.

Contact resistance is becoming an increasing performance limiter as complimentary metal oxide semiconductor devices are scaled. Non-equilibrium Green's function transport simulations are used to evaluate contact resistivity (ρc) to silicon for metals with different density of states (DOS) distributions in k-space and different Si surface orientations. It is shown that the overlap of the metal and silicon DOS in k-space can have orders of magnitude impact to ρc, as this overlap determines whether the low resistivity transverse valleys will conduct. Thus, technologists and materials researchers should search for contact metals with a DOS distribution overlapping the silicon Δ valleys as well metals with low barriers.