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The effects of Zr composition on the crystallization behaviors and reliability characteristics of atomic-layer-deposited Hf1-x ZrxOy (0 ≤ x ≤ 1) gate-dielectric films are examined. n-Channel metal-oxide-semiconductor field-effect transistor (nMOSFET) devices with ZrO2 gate dielectrics showed a much smaller Vth shift under the positive bias stress compared with the same device with HfO2 gate dielectrics. The impact of Zr composition on the crystallization temperature, crystalline phases, and surface morphology of Hf1-x ZrxOy films is studied. As the Zr composition in the Hf1-x ZrxOy films increased, the reduction of crystallization temperature and the transformation from a monoclinic to a tetragonal phase were observed. The grain size of the crystallized ZrO2 film is much smaller than that of crystallized HfO2. The Hatband voltage (Vfb) shift under positive gate-bias stress in p-channel MOS capacitor (pMOSCAP) devices show a similar trend to the Vth shift in nMOSFET devices. In addition, the annealed ZrO2 films show a large reduction in the Vfb, shift under the positive bias stress compared with as-deposited ZrO2 in pMOSCAP devices. The improved bias-temperature-instability characteristics of ZrO2 compared with that of HfO2 is related to the smaller grain size of crystallized ZrO2.

The effect of nitrogen incorporation on the dielectric properties and bias temperature instability characteristics of HfOxNy and ZrOxNy were investigated. The incorporated nitrogen induces a reduction in the capacitance equivalent oxide thickness value, increases the leakage current, and causes the turn around of Vth shift under the positive bias stress in nMOSFET. In addition, compared to HfOxNy, ZrOxNy shows a significantly lower initial Vth shift under positive gate stress due to the lower number of shallow bulk traps related to oxygen vacancies.

This letter examines the turn-around effect of a threshold voltage (Vth) shift of an n-type transistor with atomic-layer-deposited HfOxNy gate dielectrics under a positive gate bias. Vth shifted to the positive voltage direction during the first second due to electron trapping at the preexisting trap sites in the gate dielectrics, which then shifted to the negative voltage direction. This turn-around effect was attributed to hole trapping originating from the generation of electron-hole pairs by the surface plasmon or impact ionization.

We have successfully integrated a mass production worthy MIM capacitor on gate polysilicon (MIM-COG) structure using HfO2/HfOxCyNz/HfO2(HNH) dielectric for the analog/RF/mixed signal application. The insertion of HfOxCyNz into HfO2 films can successfully suppress the crystallization. As a result, HNH film shows superior breakdown and VCC-a characteristics compared to HfO2-AI2O3 multilayer stack. In addition, we suggest novel MIM-COG structure, which can solve metal routing issues in integration of conventional MIM capacitors. Also, by utilizing the MIM COG structure, the total number of mask can be reduced. Finally, MIM-COG structure with HNH dielectric shows high capacitance density (8.3fF/um2) and low VCC-a (700 ppm/V2). Moreover, excellent operation voltage for 10 year lifetime of MIM-COG structure with HNH (4.6 V) is achieved.

Novel high-k MIM capacitor technology for mixed-signal/RF applications has been successfully developed by introducing multilayered high-k dielectric(Ta/sub 2/O/sub 5//HfO/sub 2//Ta/sub 2/O/sub 5/) and NH/sub 3/ plasma electrode-dielectric interfaces treatments. For the first time, we have simultaneously achieved high capacitance of 4fF/um/sup 2/ and low leakage current of 100nA/cm/sup 2/ at high temperature of 125/spl deg/C with ultra low VCC(a=16.9ppm/V/sup 2/, b=5.2ppm/V) and high Q(/spl sim/107 at 2.4GHz and 5.4pF).

This study examined the positive bias temperature instability (PBTI) of n-type metal-oxide-semiconductor field effect transistor (nMOSFET) characteristics and the negative bias temperature instability (NBTI) of p-type metal-oxide-semiconductor field effect transistor (pMOSFET) characteristics of HfO 2 gate dielectrics with a metal gate. The interface trap charge (one) and bulk oxide trap charge (ΔN ot ) densities were separately estimated to determine the defects responsible for the threshold voltage (V th ) shift during the BTI stress. The contribution of ΔN it to the V th shift for nMOSFET PBTI and pMOSFET NBTI was ~5 and ~30%, respectively. In addition, the estimated activation energy (E a ) of ΔN it and ΔN ot was 0.10 and 0.03 eV, respectively, for nMOSFET PBTI, and 0.11 and 0.17 eV, respectively, for pMOSFET NBTI. It was confirmed that the main degradation mechanism of nMOSFET PBTI is related to the generation of oxide trap charges. However, the degradation under pMOSFET NBTI stress is due to the generation of both interface states and oxide trap charges. By measuring the stress and recovery characteristics under various bias conditions, it was also found that the electron trapping/detrapping characteristics are dominant in the nMOSFET, whereas the generation of both hole trapping/detrapping and interface states competitively occurs in the pMOSFET.

The dielectric properties and bias temperature instability characteristics of in situ nitrogen incorporated ZrO x N y gate dielectrics were compared with those of ZrO 2 , HfO 2 , and HfO x N y . ZrO x N y showed a much smaller capacitance equivalent oxide thickness (1.43 nm) than ZrO 2 (2.13 nm) and exhibited a turn-around effect under a positive gate stress bias in n-type metal oxide semiconductor field-effect transistor, which is consistent with HfO x N y . However, compared to HfO x N y , ZrO x N y showed a significantly lower initial V th shift under a positive gate stress bias due to the lower number of shallow bulk traps related to oxygen vacancies.