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Real-time image processing requires high computational and I/O throughputs obtained by use of optoelectronic system solutions. A novel architecture that uses focal-plane optoelectronic-area I/O with a fine-grain, low-memory, single-instruction-multiple-data (SIMD) processor array is presented as an efficient computational solution for real-time hyperspectral image processing. The architecture is evaluated by use of realistic workloads to determine data throughputs, processing demands, and storage requirements. We show that traditional store-and-process system performance is inadequate for this application domain, whereas the focal-plane SIMD architecture is capable of supporting real-time performances with sustained operation throughputs of 500-1500 gigaoperations/s. The focal-plane architecture exploits the direct coupling between sensor and parallel-processor arrays to alleviate data-bandwidth requirements, allowing computation to be performed in a stream-parallel computation model, while data arrive from the sensors.

Advances in VLSI and optoelectronic multichip module technologiesare enabling the construction of ultracompact massively parallelprocessing systems. The technological parameters that define thewirability and delay characteristics of these technologies have asignificant impact on the system architecture. An analytical modelis presented that allows the design space exploration of theinterconnection networks associated with multinode chips packaged on asingle multichip module substrate. Possible system designs areevaluated for a two-level interconnect with separate k-aryn-cube networks for interchip and intrachipcommunication. The impact of several architectural andtechnological parameters on the optimal network implementation (based on average no-load latency) is analyzed.