Search

High-performance pentace organic thin-film transistors (OTFTs) with room-temperature-processed Hf0.13 La0.87O as gate dielectric and Pd as gate electrode have been fabricated on both rigid Si and flexible polymide (PI) substrates. The OTFT on PI (Si) can achieve a high carrier mobility of 10.3 cm2V−1s−1 (12.5 cm2V−1s−1), and has a negligible hysteresis of −0.17 V (−0.08 V), small sub-threshold swing of 0.12 V/dec (0.11 V/dec) and low threshold voltage of −0.65 V (−0.86 V). After the devices have been exposed to the air for 30 days without encapsulation, their carrier mobilities degrade by less than 10%, indicating that the devices have good stability in the air.

A SiC high-k (HK) split-gate (SG) MOSFET is proposed with a Schottky barrier diode (SBD) integrated between the split gates, and is investigated by numerical TCAD simulation. Results show that it has the same breakdown voltage as the SiC high-k (HK) MOSFET with an optimized and practical k value of 30 for its insulation pillar, which results in the highest breakdown voltage (1857 V). The forward voltage (VF) and reverse recovery charge (QRR) of the device are 0.9 V and 3.49 $\mu \text{C}$ /cm2 respectively, much lower than those of the SiC HK MOSFET due to the SBD. Moreover, lower reverse transfer capacitance (CRSS), smaller gate charge (QG), and smaller gate-to-drain charge (QGD) are achieved for the proposed device because of the split-gates, leading to much lower switching power loss when compared with the SiC HK MOSFET. All these results indicate that the SiC HK SG-MOSFET has promising potential in future power electronics applications.

Few-layered molybdenum disulfide (MoS2) has demonstrated promising advantages for the integration of next-generation electronic devices. A vertical short-channel MoS2 transistor with a channel leng...

Uniform Hf0.5Al0.5O top-gate (TG) dielectric can be grown directly on the MoS2 surface using a high/low-temperature deposition method, and excellent performances for few-layer (FL) MoS2 transistors with Hf0.5Al0.5O as TG dielectric can be achieved: high mobility of 90 cm2/Vs, small sub-threshold swing of 77 mV/dec and low interface-state density of $1.08\times {10}^{{12}}$ eV−1cm−2. The involved mechanisms lie in the facts that (1) the TG dielectric can prevent the MoS2 surface from absorbing the oxygen and moisture in the air; (2) growing the Hf0.5Al0.5O dielectric at low temperature can well provide nucleation sites for its subsequent high-temperature growth; and (3) doping Al into HfO2 can reduce the trap charges in the resulting HfAlO dielectric to weaken the Coulomb scattering and also produce densified and uniform dielectric film. Therefore, the Hf0.5Al0.5O TG-dielectric structure and its growth method described in this work have a high potential to fabricate high-performance FL MoS2 field-effect transistors for practical electron device applications.

Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with HfLaO as high-k gate dielectric have been fabricated, and p-type silicon wafers with resistivities of 0.001 ~ 0.002, 0.005, 0.02 ~ 0.021 and $5\sim 10\Omega \cdot $ cm are used as their gate electrodes. The carrier mobility of the samples show an increase with increasing gate acceptor concentration, indicating that the TFT performances are affected by the hole concentration in the gate electrode. The HfLaO gate dielectric is highly polarizable and so produces surface-optical phonons, which can scatter the electrons in the IGZO channel to reduce their mobility. Therefore, this work directly demonstrates that the holes in the gate electrode can have a screening effect to suppress this remote phonon scattering of the gate dielectric on the channel carriers, just like the electrons in the metal gate, ITO gate and n-silicon gate of field-effect transistors.

Ge-based MOS capacitor with HfTiON/(LaON/Si) gate stacks and fluorine-plasma treatment (FPT) has been well investigated by transmission electron microscopy (TEM), electrical measurements and X-ray photoemission spectroscopy (XPS) in this work. Electrical measurements have shown that fluorine-plasma treated Ge MOS capacitor exhibits negligible hysteresis (15 mV), small gate leakage current (3.66 × 10−6 A/cm2 at Vfb + 1 V), and low interface-state density at midgap (3.2 × 1011 cm−2 eV−1). TEM results indicate that high quality LaSiON/Ge interfaces. XPS results further reveal the presence of fluorine incorporation and the less content of the Ge oxides at the LaSiON/Ge interface. These improvements should be attributed to the LaSiON passivation layer and FPT can suppress the formation of volatile and unstable Ge oxides. In addition, LaSiON passivation layer can further block inter-diffusion of elements between HfTiON and Ge substrate, and FPT can occupy the oxygen vacancies and reduce interface traps in the HfTiON dielectric and LaSiON/Ge interface. These greatly improve the performance of the Ge MOS device.

The effects of treating the HfO2 gate dielectric in different plasmas (O2, N2, and NH3) on the electrical characteristics of a back-gated MoS2 transistor are investigated. It is found that the electrical properties of the device improved after HfO2 is treated by these plasmas, in which NH3-plasma treatment results in the best electrical characteristics: high ON–OFF ratio of $1.26\times 10^{{7}}$ , high extrinsic carrier mobility of 61.5 cm2/ $\text{V}\cdot \text{s}$ , small subthreshold swing (SS) of 111 mV/dec, low interface-state density of $2.79\times 10^{12}$ eV $^{-{1}}\,\,\cdot $ cm−2, and small hysteresis of 43 mV. These should be attributed to the incorporation of more N into the HfO2 film by the NH3 plasma to repair the oxygen vacancies and increase the $k$ value of the HfO2 film. Moreover, H from the NH3 plasma effectively passivates the dangling bonds at/near the HfO2/MoS2 interface, thus creating an excellent MoS2/HfO2 interface.

In the financial industry, identifying useful information from big data becomes a key research topic. Since the vast number of technical indicators can be captured nowadays, the indicator selection can be used to support investment decision for different financial products concurrently; however, this process is still required experience from investors. In this article, we propose a novel recommendation system which is incorporated with technical indicators. The method of fuzzy subset selection is used to feature relevant indicators which have more impact to the variation in the transaction history. The proposed method enables automatic customization of indicators for different financial products in different markets. In particular, the least absolute distance fuzzy regression with non-symmetric lower and upper bounds is proposed to avoid extreme values in dominating the model. Furthermore, to reduce computational complexity in the subset selection, the selection algorithm operates in the frequency domain for identifying and matching key patterns and peaks in transacted volumes with the technical indicators. This method performs very effective although the number of factors is much greater than the sample size. The proposed method can benefit participants in the finance markets to customize their own trading dashboard as well as set up their own trading strategies.

ALD Al2O3 films treated respectively by N2, O2 and NH3 plasmas are used as gate dielectrics to fabricate few-layered MoS2 FETs. As compared with the control sample without any plasma treatment, the devices with different plasmas treatments achieve better electrical properties, with the NH3-treated device having the best results: highest carrier mobility of 39.3 cm2/Vs (~1.65 times higher than that of the control sample), smallest subthreshold swing of 90.9 mV/dec, largest on/off ratio of 1.5 × 107 and negligible hysteresis. These are attributed to the fact that the NH3 plasma treatment can (1) effectively passivate the oxygen vacancies in Al2O3 and decrease the dangling bonds at the Al2O3 surface, thus reducing the traps at/near the Al2O3/MoS2 interface; (2) increase the k value of the dielectric by N incorporation to enhance the screening effect on the Coulomb impurity scattering. In addition, these plasma treatments can adjust the MoS2 FET from depletion mode to enhancement mode by introducing negative ions into the gate dielectric.

Bottom-gated pentacene organic thin-film transistors (OTFTs) were fabricated on p-type and n-type Si wafers with different resistivities, with NdTaON as a high- ${k}$ gate dielectric. Although the pentacene grain size and dielectric surface roughness were nearly the same for all the samples, the carrier mobility improved with decreasing resistivity for both types of OTFTs (p-gate and n-gate), indicating that similar to the electron concentration, the hole concentration in the gate electrode can also affect the carrier mobility. This is attributed to the remote phonon scattering of the high- ${k}$ gate dielectric on the channel carriers, which can be screened by the holes in the gate electrode. The p-gate and n-gate samples with the lowest gate–electrode resistivity of $0.005~\Omega \cdot $ cm achieve the highest mobility of 1.15 and 1.37 cm $^{{2}}/\text{V}\cdot \text{s}$ , respectively. Moreover, for the same gate-doping concentration, the p-gate sample shows lower mobility than the n-gate sample. This is likely because under a negative gate voltage ( ${V}_{g}$ ), the p-gate is depleted to make the actual ${V}_{g}$ smaller than the applied ${V}_{g}$ , thus resulting in a lower extracted carrier mobility. In addition, such a depletion effect leads to a lower hole concentration near the gate–electrode/gate–dielectric interface, thus weakening the gate screening effect on the remote phonon scattering.

The effects of trapped charges in gate dielectric and high- ${k}$ encapsulation layer on the performance of MoS2 transistor are investigated by using SiO2 with different thicknesses as the gate dielectric and HfO2 as the encapsulation layer of the MoS2 surface. Results indicate that the positive trapped charges in SiO2 can increase the electrons in MoS2 for screening the scattering of charged impurity (CI) in SiO2 and at the SiO2/MoS2 interface to increase the carrier mobility. However, the CI scattering becomes stronger for thicker gate dielectric with more trapped charges and can dominate the electron screening effect to reduce the mobility. On the other hand, with the HfO2 encapsulation, the OFF-currents of the devices greatly increase and their threshold voltages shift negatively due to more electrons induced by more positive charges trapped in HfO2. Moreover, the screening effect of these electrons on the CI scattering results in a mobility increase, which increases with the magnitude of the CI scattering. A 51% improvement in mobility is obtained for the sample suffering from the strongest CI scattering, fully demonstrating the effective screening role of high- ${k}$ dielectric on the CI scattering.

In order to improve the hygroscopic property of LaON and also maintain its excellent interface quality with Ge, LaON incorporated with Ta is proposed and its hygroscopic and electrical properties are investigated by using dry and wet annealing. It is found that large improvement in hygroscopic property can be obtained by the Ta incorporation, and also the LaTaON film exhibits excellent interface quality with the Ge substrate due to the capability of TaON in blocking elemental inter-diffusions and also the passivation effect of LaGeOxNy formed at the LaTaON/Ge interface. Therefore, LaTaON can be considered as a high-quality gate dielectric in Ge MOS device to achieve excellent interfacial and electrical properties, e.g. in this work: high k value (21.0), low interface-state density (5.94 × 1011 cm−2 eV−1), low gate leakage current (3.07 × 10−4 A/cm2 at Vg = Vfb + 1 V) and high resistance against moisture absorption.

The effects of source/drain (S/D) electrode material (Ni, Pt and Pd) and deposition method (electron-beam evaporation and sputtering) on the performance of pentacene organic thin-film transistor (OTFT) are studied. Experimental results show that the OTFT with Pd S/D electrodes deposited by sputtering exhibits the best electrical performance. This should be due to the small charge-injection barrier at the pentacene/electrode interface and small thermal load generated during the metal deposition. Besides, through varying the Pd S/D electrode thickness, it is found that increasing the electrode thickness results in performance degradation due to degraded pentacene/electrode interface, which is caused by higher thermal stress developed during longer deposition time.

Few-layered molybdenum disulfide (MoS

To avoid surface damage of a MoS

Bottom-gated pentacene organic thin-film transistors with LaTiON gate dielectrics annealed at two different temperatures are fabricated on n+Si wafers. Although atomic-force microscopyresults indicate a smoother dielectric surface and larger pentacene grains for the sample annealed at 400 °C, this sample shows lower carrier mobility than the one annealed at 200 °C. Moreover, the crystallinity of the gate dielectrics is not a key factor in the degradation of the carrier mobility because both dielectrics remain amorphous according to TEM. However, the TEM results show that the sample annealed at 400 °C has a thicker dielectric/Si-gate interlayer. The resultant increase in gate electrode-to-dielectric distance weakens the gate screening of the remote phonon scattering, thereby degrading the mobility of the carriers in the pentacene channel. This effect can be further supported by two similar samples fabricated on n-Si wafers, in which the gate electrode with lower electron concentration has a reduced screening effect on the remote phonon scattering and results in a larger reduction in mobility for the 400 °C-annealed sample with thicker interlayer.

Bottom-gated pentacene organic thin-film transistors (OTFTs) with NdTaON as high-k gate dielectric have been fabricated on substrates with different resistivities: $0.005~\Omega ~ \cdot $ cm, $0.3~\sim ~0.9~\Omega ~ \cdot $ cm, and $1~\sim ~5~\Omega ~\cdot $ cm for n-Si wafers, and $35~\Omega $ /sq for ITO-coated glass. On the three n-Si substrates, the dielectric surface roughness and pentacene grain size are nearly the same, but the carrier mobility of the OTFTs show an obvious increase with decreasing resistivity, indicating that the gate electron concentration can affect the device performance. Despite the much larger dielectric surface roughness and smaller pentacene grain size, the OTFT on the ITO-coated glass shows the highest carrier mobility. These effects are attributed to remote phonon scattering on the channel carriers, which has been strongly screened by the electrons in the gate electrode. According to the measurement on the mobility degradation at high temperature, the remote phonon scattering is determined to be the dominant factor affecting the carrier mobility. As a result, the OTFT on ITO glass can achieve a high carrier mobility of 2.43 cm2/V $\cdot $ s and a small threshold voltage of −0.10 V.

An investigation on the incorporation of two different kinds of high-κ dielectrics (HfO2 and Ta2O5) in the dielectric of Pd-WO3-SiC Schottky diode is presented. It is found that while the surface morphology of the WO3 and WHfO films is almost the same, the WTaO film has the smoothest surface due to suppression of oxygen vacancies in WO3 by the Ta incorporation, as supported by XPS analysis. The current-voltage characteristics are examined under a wide range of temperature and hydrogen concentration. Upon exposure to 10,000 ppm H2/air, the diodes based on WHfO and WTaO show a maximum hydrogen response of 89 and 147 respectively, both higher than that (31) of the control sample with WO3. From the kinetics analysis, it is demonstrated that more hydrogen atoms are accumulated at the Pd/WHfO and Pd/WTaO interfaces than their Pd/WO3 counterpart due to larger enthalpy change for hydrogen adsorption on passivated surface, resulting in a greater barrier-height variation at the interface and thus better sensing performance for the two devices with ternary oxide.

The properties of metal-hydroxyl (M-OH) and InO x defects in InGaZnO (IGZO) and their influences on the performance of IGZO thin-film transistor (TFT) are investigated. The defects in the IGZO film are intentionally modulated by using various postmetallization-annealing (PMA) treatments. PMA is effective to densify the IGZO film and thus suppress the formation of M-OH. On the other hand, the PMA also leads to the formation of InO x near the edge of conduction channel. It is found that M-OH acts as deep-level acceptor like trap and has a heavy influence on the off-current, threshold voltage, and subthreshold swing of the TFT. On the other hand, InO x acts as shallow-level donor and mainly affects the carrier mobility of the TFT. The effects of M-OH and InO x on the TFT performance decrease and increase, respectively, with decreasing the channel length.

The effects of La content in HfLaO gate dielectric on the performance of pentacene organic thin-film transistor (OTFT) fabricated on Si have been studied. The OTFT with Hf0.103La0.897O y gate dielectric shows high performance such as high carrier mobility of 3.45 cm $^{\textsf {2}}\cdot \textsf {V}^{-\textsf {1}}\cdot \textsf {s}^{-\textsf {1}}$ (132 times and 40 times higher than those of devices using Hf oxide and La oxide, respectively), small threshold voltage of −2.09 V, and negligible hysteresis of −0.029 V. Binding-energy shift of Hf 4f peak in the X-ray photoelectron spectroscopy spectrum indicates that La incorporation can passivate the oxygen vacancies in HfO2. Atomic force microscope reveals that the La incorporation can reduce the surface roughness of the gate dielectric by suppressing the crystallization of HfO2. Therefore, by using Hf0.103La0.897O y as gate dielectric, OTFT with high carrier mobility and small threshold voltage can be obtained.

The electrochemical reactions of SiC film with Li+ have been investigated by electrochemical characterization and X-ray photoelectron spectroscopy. The SiC film is prepared by inductively-coupled-plasma chemical-vapor-deposition (ICP-CVD) technique and displays an amorphous state due to the low processing temperature (∼350 °C). An irreversible reaction of SiC with Li+ occurs with the formation of lithium silicon carbide (LixSiyC) and elemental Si, followed by a reversible alloying/dealloying reaction of the elemental Si with Li+. The 500 nm SiC film shows an initial reversible specific capacity of 917 mA h g−1 with a capacity retention of 41.0% after 100 cycles at 0.3C charge/discharge current, and displays much better capacity retention than the Si film (5.2%). It is found that decreasing the SiC thickness effectively improves the specific capacity by enhancing the reaction kinetics but also degrades the capacity retention (for 250 nm SiC, its initial capacity is 1427 mA h g−1 with a capacity retention of 25.7% after 100 cycles). The better capacity retention of the 500 nm SiC anode is mainly because residual SiC exists in the film due to its incomplete reaction caused by its lower reaction kinetics, and it has high hardness and can act as a buffer matrix to alleviate the anode volume change, thus improving the mechanical stability and capacity retention of the SiC anode.

GaAs metal–oxide–semiconductor capacitors with NdTaON as gate dielectric and NdAlON, NdON or AlON as interfacial passivation layer (IPL) are fabricated, and their interfacial and electrical properties are compared with their counterpart without IPL. Experimental results show that owing to the suppressed hygroscopicity of NdON by Al incorporation, best improvements in electrical properties and reliability are achieved for the sample with NdAlON IPL (low interface-state density ( $8 \times 10^{11}$ cm−2/eV), small flatband voltage (0.72 V), negligible hysteresis (43 mV), small frequency dispersion, and low gate leakage current density ( $2.56 \times 10^{-6}$ A/cm2 at Vfb + 1 V). These should be attributed to suppressed growth of unstable Ga and As oxides on the GaAs surface and reduced in-diffusion of elements from the gate dielectric to the GaAs surface by the NdAlON IPL during gate-dielectric annealing.

The resonance between the plasmons in gate electrode and the phonons in gate oxide of the omnipresent metal–oxidesemiconductor devices predicted in 2004 is experimentally demonstrated to degrade the mobility of the carriers in the semiconductor channel. By using bottom-gated pentacene organic thin-film transistors fabricated on n-type Si substrates with different resistivities, this work experimentally shows that even for thick HfLaO gate dielectric (~50 nm), the interaction between the gate plasmons and the dielectric phonons can significantly affect the carrier mobility. FTIR and Raman spectra reflect that the phonon frequency of the dielectric ranges from 13.2 to 24.9 THz, overlapping the gate-plasmon frequency (13.2 ~ 18.7 THz) of the 0.01 ~ 0.015 Ω·cm substrate. Therefore, the predicted mobility reduction can be explained by a simpler concept of “resonance”: when the oscillations of gate carrier and dielectric atom have about the same frequency, the remote phonon scattering of the gate dielectric on the channel carriers is greatly enhanced to reduce their mobility. In summary, this resonance-induced mobility reduction could pose a temperature-related reliability problem to electronic circuits when carrier freeze-out at low working temperature reduces the carrier density in the gate electrode to about 3 × 1018 cm−3 to result in a plasmon frequency close to the phonon frequency of the gate dielectric.

Room-temperature-processed amorphous InGaZnO thin-film transistors (TFTs) with three different semiconductors (Si, GaAs, and Ge) of various doping concentrations as gate electrodes are fabricated. Like the conventional Si gate devices, both their GaAs and Ge counterparts show carrier mobility increasing with increasing gate doping concentration, further supporting that the holes at/near the surface of a p-type gate electrode can have a screening effect on the remote phonon scattering caused by the surface phonons of their high-k gate dielectrics. Moreover, for the same gate doping concentration, the Ge gate device has a carrier mobility about three times that of its conventional Si gate counterpart. This implies that lower-mass charge carriers in the gate electrode could have a stronger screening effect on remote phonon scattering. As a result, even with a moderate gate doping concentration of 1.0 × 1018 cm−3, the room-temperature-processed Ge gate device shows a high carrier mobility of 60.8 cm2/V s. The enhanced screening effect of the Ge gate electrode should be due to its higher-energy plasmons, which could couple more strongly with the phonons of the gate dielectric to result in weaker gate-dielectric vibration.

Ge metal–oxide–semiconductor capacitor with HfTiON/TaYON stacked gate dielectric treated by fluorine plasma is fabricated, and its interfacial and electrical properties are compared with its counterparts without the TaYON interfacial passivation layer or the fluorine-plasma treatment. Experimental results show that the sample exhibits excellent performances: low interface-state density ( $2.5\times 10^{11}$ cm $^{-2}$ eV $^{-1})$ , small flatband voltage (0.34 V), good capacitance–voltage behavior, small frequency dispersion, and low gate leakage current ( $2.47 \times 10^{-5}$ A/cm2 at $\text{V}_{\text {g}} = \,\, \text{V}_{\text {fb}} + 1$ V). These should be attributed to the suppressed growth of unstable Ge oxides on the Ge surface during gate dielectric annealing by the TaYON interlayer and fluorine incorporation, thus greatly reducing the defective states at/near the TaYON/Ge interface and improving the electrical properties of the device.

A hydrogen sensor based on pentacene organic thin-film transistor (OTFT) with palladium (Pd) source and drain (S/D) electrodes is analyzed in detail. When exposed to H2 with different concentrations, the sensor shows a clear change in drain current due to three reasons: 1) work-function change of the source electrode induced by hydrogen absorption; 2) reduced carrier mobility; and 3) increased S/D series resistance both caused by the expansion of the S/D electrodes after absorbing hydrogen. Analysis of the data demonstrates that the first two are the dominant mechanisms. Without the need of heating, rapid, reversible, and concentration-dependent response of the OTFT is observed upon introduction and removal of H2 with concentration ranging from 200 to 17 000 ppm.

Bottom-gate pentacene organic thin-film transistors (OTFTs) with HfLaO gate dielectric have been fabricated on different substrates with different gate materials (namely, Ti- or Al-coated vacuum tape, n-Si wafer, and ITO-coated glass) and the effects of the gate material on device performance have been studied. Although the dielectric surface and pentacene grain on the Ti- and Al-coated vacuum tapes are much rougher and much smaller, respectively, than those on the n-Si wafer, the OTFTs fabricated on the two vacuum tapes have much higher carrier mobility than that fabricated on the n-Si wafer, implying that the gate material can greatly affect the device performance. Like the case for MOSFET, the possible reason is that metal gate can screen the remote phonon scattering of HfLaO and avoid the remote Coulomb scattering of silicon gate, thus resulting in higher carrier mobility for the OTFTs with Al and Ti gate electrodes. As a result, a high-performance OTFT with a carrier mobility of 4.95 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ and threshold voltage of −1.31 V was successfully fabricated on vacuum tape by using Ti gate.

ZrON gate-dielectric GaAs metal–oxide–semiconductor capacitors with a LaSiON interfacial passivation layer (IPL) and different fluorine-plasma-treatment methods are fabricated and investigated. Compared to using plasma-treating a GaAs surface or no plasma treatment, the sample with plasma-treated IPL exhibits the lowest interface-state density ( ${1.08 \times 10^{12}}$ cm−2eV−1), highest ${k}$ value (18.3) and smallest gate-leakage current ( ${1.62 \times 10^{-5}}$ A/cm2 at ${V_{fb}}$ + 1 V). The fact that plasma-treating IPL can effectively reduce the defect-related Ga/As–O and As–As bonds at GaAs surface and also incorporate more F into the gate stack to passivate the defects in it and at/near IPL/GaAs interface should be responsible for these.

GaAs MOS capacitors with ZrTiON high- ${k}$ gate dielectric and ZrLaON or ZrON as interfacial passivation layer (IPL) are fabricated, and their electrical properties are investigated. As compared with a control sample without IPL, improved interfacial quality and electrical properties are obtained for both samples, with the ZrTiON/ZrLaON/GaAs device, exhibiting the lowest interface-state density ( $1.1 \times 10^{12}$ cm $^{-2}$ eV $^{-1})$ , smallest gate leakage current density ( $1.62 \times 10^{-5}$ A cm $^{-2}$ at $V_{g} =V_{{\text {fb}}} + 1$ V), and largest equivalent dielectric constant (25.1). All of these should be attributed to the fact that incorporating La into the ZrON IPL can: first, passivate its defects and, second, enhance the blocking role of the IPL against the Ti/O in-diffusion to the GaAs substrate and the Ga/As out-diffusion to the high- ${k}$ , thus resulting in an obvious reduction of relevant defects in the gate stack and also suppressing the formation of unstable Ga/As oxides and As–As dimer at the GaAs surface to obtain a much improved dielectric/GaAs interface.

GaAs metal–oxide–semiconductor capacitors are fabricated by alternately depositing La oxynitride (LaON)/TiON or TiON/LaON or first depositing a LaON interlayer and then alternately depositing LaON/TiON, and their interfacial and electrical properties are investigated and compared. Experimental results show that the sample with LaON interlayer exhibits better interface quality and electrical performance than the other two samples: lower interface-state density ( $1.05 \times 10^{12}$ cm $^{-2}$ eV $^{-1})$ , smaller gate leakage current ( $2.33 \times 10^{-5}$ A/cm2 at $\text{V}_{\mathrm {fb}} + 1$ V), larger equivalent dielectric constant (25.3), and better high-field reliability. The involved mechanism lies in the fact that the LaON interlayer on the GaAs surface can effectively reduce the defective states at/near the interface by blocking the Ti/O in-diffusion and As/Ga out-diffusion, thus improving the interfacial and electrical properties of the device.

Pentacene organic thin-film transistors (OTFTs) using La x Nb(1– x )O y as gate dielectric with ${x}= \mathsf {1}$ , 0.946, 0.850, and 0.648 have been fabricated on vacuum tape at a temperature of 200 °C. Among them, the OTFT with La0.850Nb0.150O y as gate dielectric has the highest carrier mobility of 4.63 cm $^{\mathsf {2}}\text{V}^{\mathsf {-1}}\text{s}^{\mathsf {-1}}$ , negligible hysteresis of −0.032 V, small subthreshold swing of 0.174 V/decade, and small threshold voltage of −1.90 V. AFM and X-ray photoelectron spectroscopy reveal that Nb incorporation can alleviate the hygroscopicity of La oxide, resulting in a smoother dielectric surface. Pentacene grain size first increases with Nb content due to smoother dielectric surface, and then decreases due to Nb-induced traps acting as nucleation sites for the growth of pentacene grains on the dielectric surface. Therefore, there exists an optimal Nb content in La x Nb(1– x )O y that can result in the largest grain size and, hence, the highest carrier mobility.

The carrier mobility of MoS2 transistors can be greatly improved by the screening effect of high-k gate dielectric. Therefore, in this paper, atomic layer deposited HfTiO annealed in different ambients (N2, O2, and NH3) is used to replace SiO2 as gate dielectric for fabricating back-gated multilayer MoS2 transistors. As a result, excellent electrical properties are achieved for the sample annealed in NH3 at 400 °C for 10 min: the field-effect mobility of 31.1 cm $^{\mathrm {\mathbf {2}}}$ /(V $\cdot $ s) and the subthreshold swing of 100 mV/decade, which are six times higher and three times smaller compared with that of the control sample, respectively. The enhanced electrical performance should be associated with the passivation effects of the NH3 annealing, which reduces defective states in the HfTiO dielectric and at/near the HfTiO/MoS2 interface. The capacitance equivalent thickness of the gate dielectric (HfTiO) is only 6.79 nm, which is quite small for back-gated MoS2 transistor and is conducive to the scaling down of the device.

La2O3 and Y2O3 are used as gate dielectric in Ge MOS capacitors, and their electrical and interfacial properties are comparatively studied. Due to the much higher reactivity of La2O3 with Ge than Y2O3, thicker germanate interlayer is formed, leading to better interface quality for the former. Moreover, it is found that N incorporation in the oxides reduces the formation of both germanate and GeO x , with much more obvious effect for La2O3 and thus the best interface quality (a low interface-state density of $4.96\times 10^{11}$ cm $^{-2}$ eV $^{-1})$ , which gives promising electrical properties: large equivalent dielectric constant (18.8), small flat-band shift (0.37 V), low gate leakage current ( $2.89 \times 10^{-4}$ A/cm2 at $V_{g} = V_{\mathrm{ fb}}+ 1$ V), and high reliability under electrical stress.

In this work, we investigate the effects on the electrical properties of few-layered MoS

Bottom-gate pentacene organic thin-film transistors (OTFTs) with different gate electron concentrations and pentacene thicknesses are fabricated. The performances of the OTFTs show dependence on both gate electron concentration and pentacene thickness. Electrons in the gate electrode can reduce the effect from surface optical phonons of the high-k gate dielectric (NdTaON), and so higher gate electron concentration gives better device performance. It is also supported by measurements at 140°C, where the remote phonon scattering is enhanced. Moreover, it is found that the extracted carrier mobility decreases with increasing pentacene thickness, which is attributed to the series resistance of the source/drain electrodes.

Improvement in the performance of pentacene organic thin-film transistor has been demonstrated by using fluorine plasma-treated or ion-implanted HfO 2 as its gate dielectric. The carrier mobility of the OTFT on HfO 2 with 900-s plasma treatment can reach a carrier mobility of 0.662 cm2/Vs, about 7 times higher than that of the control sample without fluorine incorporation. The reason is larger pentacene grains due to trap passivation, smoother surface and higher surface energy. On the other hand, the carrier mobility of the OTFT on HfO 2 with a fluorine implant dose of (1 ×10)14/cm2 is improved to 0.251 cm2/Vs, about 2.7 times higher than that of the control sample. The smoother surface of the gate dielectric with fluorine implant results in the growth of larger pentacene grains, leading to an increase of carrier mobility. However, excessive fluorine implant dose or plasma treatment time could cause damage to the gate dielectric, thus decreasing the carrier mobility of the device.

For top-gated MoS

Pentacene organic thin-film transistors (OTFTs) with very high carrier mobility have been achieved on both rigid and flexible substrates by using high-k gate dielectric and metal gate. The high-k gate dielectric with suitable thickness can reduce the surface-roughness scattering, while the metal gate can suppress the remote phonon scattering. As a result, based on NbLaO gate dielectric, OTFTs with high carrier mobility of 10.6 cm2 V−1 s−1 (7.99 cm2 V−1 s−1) with the capacitance per unit area measured at frequency of 1 kHz and small threshold voltage of −0.92 V (−0.74 V) fabricated on Pd-coated Si substrate (Pd-coated vacuum tape) are realized, though they have rougher dielectric surface and smaller pentacene grains than their counterparts fabricated on n-Si substrate. Moreover, with the addition of 13-nm SiO2 interlayer between the NbLaO gate dielectric and metal gate electrode, the carrier mobility decreases by 71% and 65% for the OTFTs on Si and V.T. substrates, respectively, highlighting the importance of the RPS.

The interfacial and electrical properties of sputtered Ti-incorporated Hf oxynitride on Ga2O3(Gd2O3) (GGO) with or without N2-plasma treated as an interfacial passivation layer (IPL) for Ge MOS capacitor are compared. It is found that low interface-state density ( $3.4 \times 10^{11}$ cm $^{-2}$ eV $^{-1}$ ), small gate leakage current ( $2.93 \times 10^{-5}$ A/cm2 at $V_{g} = V_{\mathrm{fb}} + 1$ V), small capacitance equivalent thickness (1.09 nm), and large equivalent dielectric constant (26.5) can be achieved for the sample with N2-plasma-treated GGO IPL. The involved mechanisms lie in the fact that the N2-plasma-treated GGO IPL can effectively block the interdiffusion of elements and suppress the formation of GeO x interfacial layer.

This work proposes a method for extracting the barrier height, ideality factor, series, and shunt resistances of Schottky diodes with high accuracy and consistency. By defining the voltage boundaries for the three regions of the current–voltage curve that are controlled by shunt resistance, thermal emission, and series resistance, respectively, the method can avoid the problems of traditional methods through nonlinear fitting and iterations. The application on Schottky-diode-type hydrogen sensor with a structure of Pd/WO3/SiC reveals excellent agreement between the extracted voltage boundaries and the turning points on the current–voltage curve under different temperatures and hydrogen concentrations. The average mean-squared error of the model current–voltage data vs. experimental data is 0.371, more than five times smaller than that of traditional methods based on least-squares linear regression.

A 2-D analytical threshold-voltage model for ultra-thin-body MOSFET with buried insulator and high-k gate dielectric is established by solving the 2-D Poisson's equation for the gate-dielectric, channel and buried-insulator regions. The validity of the model is confirmed by comparing with experimental data and other models. Using the model, the influences of gate-dielectric permittivity, buried-insulator permittivity, channel thickness, buried-insulator thickness and channel doping concentration on threshold behaviors are investigated. It is found that the threshold behaviors can be improved by using buried insulator with low permittivity, thin channel and high channel doping concentration. However, the threshold performance would be degraded when high-k gate dielectric is used due to enhanced fringing-field effect.