83 results on '"Wisniewski, Remigiusz"'
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2. A Polynomial-Time Algorithm for Detecting Potentially Unbounded Places in a Petri Net-Based Concurrent System
3. Preliminary Verification of Liveness in a Control Part of Cyber-Physical Systems Modeled by a Petri Net
4. Hippo-CPS: A Tool for Verification and Analysis of Petri Net-Based Cyber-Physical Systems
5. Hippo-CPS: Verification of Boundedness, Safeness and Liveness of Petri Net-Based Cyber-Physical Systems
6. Verification of the Boundedness Property in a Petri Net-Based Specification of the Control Part of Cyber-Physical Systems
7. Optimal Sensor Selection for Diagnosability Enforcement in Labeled Petri Nets
8. Implementation of Concurrent Control Systems in FPGA
9. Modelling of Concurrent Systems in Hardware Languages
10. Introduction
11. Hypergraphs and Exact Transversals
12. Prototyping of Concurrent Control Systems
13. Decomposition of Concurrent Control Systems
14. Analysis of Concurrent Control Systems
15. Perfect Graphs and Comparability Graphs
16. Related Work
17. Conclusions
18. Effective Partial Reconfiguration of Logic Controllers Implemented in FPGA Devices
19. Theoretical Aspects of Petri Nets Decomposition Based on Invariants and Hypergraphs
20. Application of Hypergraphs to SMCs Selection
21. Application of an Exact Transversal Hypergraph in Selection of SM-Components
22. Interpreted Petri Nets in Modelling and Analysis of Physical Resilient Manufacturing Systems
23. Analysis of Control Part of Cyber-Physical Systems Specified by Interpreted Petri Nets
24. Holistic Research on Blockchain’s Consensus Protocol Mechanisms with Security and Concurrency Analysis Aspects of CPS
25. Trusted and Secure Blockchain-Based Architecture for Internet-of-Medical-Things
26. Modelling of the effectiveness of integrating additive manufacturing technologies into Petri net-based manufacturing systems
27. Design of Petri Net-Based Cyber-Physical Systems Oriented on the Implementation in Field Programmable Gate Arrays
28. Partial reconfiguration of compositional microprogram control units implemented on FPGAS
29. Special Issue on Recent Advances in Petri Nets, Automata, and Discrete-Event Hybrid Systems
30. A Polynomial-Time Algorithm to Obtain State Machine Cover of Live and Safe Petri Nets
31. Determinism in Cyber-Physical Systems Specified by Interpreted Petri Nets
32. Specification of Cyber-Physical Systems with the Application of Interpreted Nets
33. Analysis and Design Automation of Cyber-Physical System with Hippo and IOPT-Tools
34. Low-Cost FPGA Hardware Implementation of Matrix Converter Switch Control
35. C-Exact Hypergraphs in Concurrency and Sequentiality Analyses of Cyber-Physical Systems Specified by Safe Petri Nets
36. Petri Net-Based Specification of Cyber-Physical Systems Oriented to Control Direct Matrix Converters With Space Vector Modulation
37. IEEE Access Special Section: Cyber-Physical Systems
38. Prototyping of Concurrent Control Systems With Application of Petri Nets and Comparability Graphs
39. Design of Multi-Context Reconfigurable Logic Controllers Implemented in FPGA Devices Oriented for Further Partial Reconfiguration
40. Safety analysis of Petri nets based on the SM-cover computed with the linear algebra technique
41. Representation of primes in the form p = 6 · x ± 1 and its application to the RSA prime factorization
42. Dynamic Partial Reconfiguration of Concurrent Control Systems Specified by Petri Nets and Implemented in Xilinx FPGA Devices
43. Representation of Primes in the Form p = 6 ∙ x ± 1 and its Application to the RSA Prime Factorization.
44. Design and Verification of Real-Life Processes With Application of Petri Nets
45. Dynamic Partial Reconfiguration of Concurrent Control Systems Implemented in FPGA Devices
46. Decomposition, validation and documentation of control process specification in form of a Petri net
47. Dual synthesis of Petri net based dependable logic controllers for safety critical systems
48. Application of comparability graphs in decomposition of Petri nets
49. Design of microprogrammed controllers with address converter implemented on programmable systems with embedded memories
50. Reduction of the memory size in the microprogrammed controllers
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