467 results on '"Witters, L."'
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2. Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET
3. Understanding and optimizing the floating body retention in FDSOI UTBOX
4. Ultimate nano-electronics: New materials and device concepts for scaling nano-electronics beyond the Si roadmap
5. Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs
6. FinFETs and Their Futures
7. Low-Voltage Scaled 6T FinFET SRAM Cells
8. Integration aspects of strained Ge pFETs
9. Superior reliability of high mobility (Si)Ge channel pMOSFETs
10. Challenges and opportunities in advanced Ge pMOSFETs
11. Growth of high Ge content SiGe on (110) oriented Si wafers
12. On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si 0.45Ge 0.55 pMOSFETs
13. Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
14. Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering
15. DC and RF Characterization of Nano-ridge HBT Technology Integrated on 300 mm Si Substrates
16. Multi-gate devices for the 32 nm technology node and beyond
17. Toward high-performance and reliable Ge channel devices for 2 nm node and beyond
18. Independent double-gate FinFETs with asymmetric gate stacks
19. Troglitazone causes acute mitochondrial membrane depolarisation and an AMPK-mediated increase in glucose phosphorylation in muscle cells
20. From 5G to 6G: will compound semiconductors make the difference?
21. FinFETs and Their Futures
22. First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering
23. Understanding and Physical Modeling Superior Hot-Carrier Reliability of Ge pNWFETs
24. Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation
25. TEM investigations of gate-all-around nanowire devices
26. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
27. High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG
28. A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
29. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
30. Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET
31. First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs
32. 3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
33. Key challenges and opportunities for 3D sequential integration
34. Semiconductor Technologies for next Generation Mobile Communications
35. Ge:B and GeSn:B Low Temperature Selective Epitaxial Growth Schemes for Source/Drain layers in Ge pMOS devices
36. Ground Plane Impact on the Threshold Voltage of Relaxed Ge pFinFETs
37. 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
38. First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs
39. Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling
40. An In-depth Study of High-Performing Strained Germanium Nanowires pFETs
41. Scalability comparison between raised- and embedded-SiGe source/drain structures for Si 0.55 Ge 0.45 implant free quantum well pFET
42. Anisotropic stress in narrow sGe fin field-effect transistor channels measured using nano-focused Raman spectroscopy
43. Editors' Choice—Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures
44. Fabrication challenges and opportunities for high-mobility materials: from CMOS applications to emerging derivative technologies.
45. The impact of sequential-3D integration on semiconductor scaling roadmap
46. Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition
47. Use of high order precursors for manufacturing gate all around devices
48. Double-gate Si junction-less n-type transistor for high performance Cu-BEOL compatible applications using 3D sequential integration
49. Low temperature influence on long channel STI last process relaxed and strained Ge pFinFETs
50. 3D technologies for analog/RF applications
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