1,187 results on '"Wong, H-S Philip"'
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2. Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory
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Wu, Xiangjin, Khan, Asir Intisar, Lee, Hengyuan, Hsu, Chen-Feng, Zhang, Huairuo, Yu, Heshan, Roy, Neel, Davydov, Albert V., Takeuchi, Ichiro, Bao, Xinyu, Wong, H.-S. Philip, and Pop, Eric
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- 2024
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3. Complementary carbon nanotube metal–oxide–semiconductor field-effect transistors with localized solid-state extension doping
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Zhang, Zichen, Passlack, Matthias, Pitner, Gregory, Natani, Shreyam, Su, Sheng-Kai, Chao, Tzu-Ang, Liew, San Lin, Hou, Vincent D.-H., Hsu, Chen-Feng, Shipley, Wade E., Safron, Nathaniel, Doornbos, Gerben, Lee, Tsung-En, Radu, Iuliana, Kummel, Andrew C., Bandaru, Prabhakar, and Wong, H.-S. Philip
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- 2023
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4. Improved Gradual Resistive Switching Range and 1000x On/Off Ratio in HfOx RRAM Achieved with a $Ge_2Sb_2Te_5$ Thermal Barrier
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Islam, Raisul, Qin, Shengjun, Deshmukh, Sanchit, Yu, Zhouchangwan, Koroglu, Cagil, Khan, Asir Intisar, Schauble, Kirstin, Saraswat, Krishna C., Pop, Eric, and Wong, H. -S. Philip
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Physics - Applied Physics ,Condensed Matter - Materials Science - Abstract
Gradual switching between multiple resistance levels is desirable for analog in-memory computing using resistive random-access memory (RRAM). However, the filamentary switching of $HfO_x$-based conventional RRAM often yields only two stable memory states instead of gradual switching between multiple resistance states. Here, we demonstrate that a thermal barrier of $Ge_2Sb_2Te_5$ (GST) between $HfO_x$ and the bottom electrode (TiN) enables wider and weaker filaments, by promoting heat spreading laterally inside the $HfO_x$. Scanning thermal microscopy suggests that $HfO_x+GST$ devices have a wider heating region than control devices with only $HfO_x$, indicating the formation of a wider filament. Such wider filaments can have multiple stable conduction paths, resulting in a memory device with more gradual and linear switching. The thermally-enhanced $HfO_x+GST$ devices also have higher on/off ratio ($>10^3$) than control devices ($<10^2$), and a median set voltage lower by approximately 1 V (~35%), with a corresponding reduction of the switching power. Our $HfO_x+GST$ RRAM shows 2x gradual switching range using fast (~ns) identical pulse trains with amplitude less than 2 V.
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- 2022
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5. Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies
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Gottscho, Richard A., Levine, Edlyn V., Liu, Tsu-Jae King, McIntyre, Paul C., Mitra, Subhasish, Murmann, Boris, Rabaey, Jan M., Salahuddin, Sayeef, Shih, Willy C., and Wong, H. -S. Philip
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Computer Science - Other Computer Science - Abstract
Semiconductor innovation drives improvements to technologies that are critical to modern society. The country that successfully accelerates semiconductor innovation is positioned to lead future semiconductor-driven industries and benefit from the resulting economic growth. It is our view that a next generation infrastructure is necessary to accelerate and enhance semiconductor innovation in the U.S. In this paper, we propose such an advanced infrastructure composed of a national network of facilities with enhancements in technology and business models. These enhancements enable application-driven and challenge-based research and development, and ensure that facilities are accessible and sustainable. The main tenets are: a challenge-driven operational model, a next-generation infrastructure to serve that operational model, technology innovations needed for advanced facilities to speed up learning cycles, and innovative cost-effective business models for sustainability. Ultimately, the expected outcomes of such a participatory, scalable, and sustainable nation-level advanced infrastructure will have tremendous impact on government, industry, and academia alike.
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- 2022
6. A compute-in-memory chip based on resistive random-access memory
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Wan, Weier, Kubendran, Rajkumar, Schaefer, Clemens, Eryilmaz, Sukru Burc, Zhang, Wenqiang, Wu, Dabin, Deiss, Stephen, Raina, Priyanka, Qian, He, Gao, Bin, Joshi, Siddharth, Wu, Huaqiang, Wong, H-S Philip, and Cauwenberghs, Gert
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Information and Computing Sciences ,Engineering ,Electronics ,Sensors and Digital Hardware ,Affordable and Clean Energy ,General Science & Technology - Abstract
Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)1 promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory2-5. Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware6-17, it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-1019 image classification, 84.7-percent accuracy on Google speech command recognition20, and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task.
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- 2022
7. Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor
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Lee, Chi-Shuen, Cline, Brian, Sinha, Saurabh, Yeric, Greg, and Wong, H. -S. Philip
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Computer Science - Emerging Technologies - Abstract
We present a DevIce-to-System Performance EvaLuation (DISPEL) workflow that integrates transistor and interconnect modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and timing analysis to evaluate system-level performance of new CMOS technologies. As the impact of parasitic resistances and capacitances continues to increase with dimensional downscaling, component-level optimization alone becomes insufficient, calling for a holistic assessment and optimization methodology across the boundaries between devices, interconnects, circuits, and systems. The physical implementation flow in DISPEL enables realistic analysis of complex wires and vias in VLSI systems and their impact on the chip power, speed, and area, which simple circuit simulations cannot capture. To demonstrate the use of DISPEL, a 32-bit commercial processor core is implemented using theoretical n-type MoS2 and p-type Black Phosphorous (BP) planar FETs at a projected 5-nm node, and the performance is benchmarked against Si FinFETs. While the superior gate control of the MoS2/BP FETs can theoretically provide 51% reduction in the iso-frequency energy consumption, the actual performance can be greatly limited by the source/drain contact resistances. With the large amount of data generated by DISPEL, a neural-network is trained to predict the key performance metrics of the 32-bit processor core using the characteristics of transistors and interconnects as the input features without the need to go through the time-consuming physical implementation flow. The machine learning algorithms show great potentials as a means for evaluation and optimization of new CMOS technologies and identifying the most significant technology design parameters., Comment: 12 pages, 23 figures
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- 2021
8. Toward Low-Temperature Solid-Source Synthesis of Monolayer MoS2
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Tang, Alvin, Kumar, Aravindh, Jaikissoon, Marc, Saraswat, Krishna, Wong, H. -S. Philip, and Pop, Eric
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Physics - Applied Physics ,Condensed Matter - Mesoscale and Nanoscale Physics ,Condensed Matter - Materials Science - Abstract
Two-dimensional (2D) semiconductors have been proposed for heterogeneous integration with existing silicon technology; however, their chemical vapor deposition (CVD) growth temperatures are often too high. Here, we demonstrate direct CVD solid-source precursor synthesis of continuous monolayer (1L) MoS$_2$ films at 560 C in 50 min, within the 450-to-600 C, 2 h thermal budget window required for back-end-of-the-line compatibility with modern silicon technology. Transistor measurements reveal on-state current up to ~140 $\mathrm{{\mu}A/{\mu}m}$ at 1 V drain-to-source voltage for 100 nm channel lengths, the highest reported to date for 1L MoS$_2$ grown below 600 C using solid-source precursors. The effective mobility from transfer length method test structures is $\mathrm{29 \pm 5\ cm^2V^{-1}s^{-1}}$ at $\mathrm{6.1 \times 10^{12}\ cm^{-2}}$ electron density, which is comparable to mobilities reported from films grown at higher temperatures. The results of this work provide a path toward the realization of high-quality, thermal-budget-compatible 2D semiconductors for heterogeneous integration with silicon manufacturing.
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- 2021
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9. Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory
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Wan, Weier, Kubendran, Rajkumar, Schaefer, Clemens, Eryilmaz, S. Burc, Zhang, Wenqiang, Wu, Dabin, Deiss, Stephen, Raina, Priyanka, Qian, He, Gao, Bin, Joshi, Siddharth, Wu, Huaqiang, Wong, H. -S. Philip, and Cauwenberghs, Gert
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Computer Science - Hardware Architecture ,Computer Science - Artificial Intelligence ,Computer Science - Emerging Technologies ,Computer Science - Machine Learning - Abstract
Realizing today's cloud-level artificial intelligence functionalities directly on devices distributed at the edge of the internet calls for edge hardware capable of processing multiple modalities of sensory data (e.g. video, audio) at unprecedented energy-efficiency. AI hardware architectures today cannot meet the demand due to a fundamental "memory wall": data movement between separate compute and memory units consumes large energy and incurs long latency. Resistive random-access memory (RRAM) based compute-in-memory (CIM) architectures promise to bring orders of magnitude energy-efficiency improvement by performing computation directly within memory. However, conventional approaches to CIM hardware design limit its functional flexibility necessary for processing diverse AI workloads, and must overcome hardware imperfections that degrade inference accuracy. Such trade-offs between efficiency, versatility and accuracy cannot be addressed by isolated improvements on any single level of the design. By co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM - the first multimodal edge AI chip using RRAM CIM to simultaneously deliver a high degree of versatility for diverse model architectures, record energy-efficiency $5\times$ - $8\times$ better than prior art across various computational bit-precisions, and inference accuracy comparable to software models with 4-bit weights on all measured standard AI benchmarks including accuracy of 99.0% on MNIST and 85.7% on CIFAR-10 image classification, 84.7% accuracy on Google speech command recognition, and a 70% reduction in image reconstruction error on a Bayesian image recovery task. This work paves a way towards building highly efficient and reconfigurable edge AI hardware platforms for the more demanding and heterogeneous AI applications of the future., Comment: 34 pages, 14 figures, 1 table
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- 2021
10. Statistical Analysis of Contacts to Synthetic Monolayer MoS2
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Kumar, Aravindh, Tang, Alvin, Wong, H. -S. Philip, and Saraswat, Krishna
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Condensed Matter - Materials Science ,Physics - Applied Physics - Abstract
Two-dimensional (2D) semiconductors are promising candidates for scaled transistors because they are immune to mobility degradation at the monolayer limit. However, sub-10 nm scaling of 2D semiconductors, such as MoS2, is limited by the contact resistance. In this work, we show for the first time a statistical study of Au contacts to chemical vapor deposited monolayer MoS2 using transmission line model (TLM) structures, before and after dielectric encapsulation. We report contact resistance values as low as 330 ohm-um, which is the lowest value reported to date. We further study the effect of Al2O3 encapsulation on variability in contact resistance and other device metrics. Finally, we note some deviations in the TLM model for short-channel devices in the back-gated configuration and discuss possible modifications to improve the model accuracy., Comment: 4 pages, 5 figures, to be published in IEEE IITC 2021 conference proceedings; fixed labels in Fig 4(b) and removed blank page at the end
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- 2021
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11. Single-crystal hexagonal boron nitride monolayer epitaxially grown on Cu (111) thin film across a wafer
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Chen, Tse-An, Chuu, Chih-Piao, Tseng, Chien-Chih, Wen, Chao-Kai, Wong, H. -S. Philip, Pan, Shuangyuan, Li, Rongtan, Zhang, Yanfeng, Fu, Qiang, Yakobson, Boris I., Chang, Wen-Hao, and Li, Lain-Jong
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Condensed Matter - Materials Science ,Condensed Matter - Mesoscale and Nanoscale Physics - Abstract
We demonstrate single crystal growth of wafer-scale hexagonal boron nitride (hBN), an insulating atomic thin monolayer, on high-symmetry index surface plane Cu(111). The unidirectional epitaxial growth is guaranteed by large binding energy difference, ~0.23 eV, between A- and B-steps edges on Cu(111) docking with B6N7 clusters, confirmed by density functional theory calculations.
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- 2021
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12. Neural Network Compression for Noisy Storage Devices
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Isik, Berivan, Choi, Kristy, Zheng, Xin, Weissman, Tsachy, Ermon, Stefano, Wong, H. -S. Philip, and Alaghi, Armin
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Computer Science - Machine Learning - Abstract
Compression and efficient storage of neural network (NN) parameters is critical for applications that run on resource-constrained devices. Despite the significant progress in NN model compression, there has been considerably less investigation in the actual \textit{physical} storage of NN parameters. Conventionally, model compression and physical storage are decoupled, as digital storage media with error-correcting codes (ECCs) provide robust error-free storage. However, this decoupled approach is inefficient as it ignores the overparameterization present in most NNs and forces the memory device to allocate the same amount of resources to every bit of information regardless of its importance. In this work, we investigate analog memory devices as an alternative to digital media -- one that naturally provides a way to add more protection for significant bits unlike its counterpart, but is noisy and may compromise the stored model's performance if used naively. We develop a variety of robust coding strategies for NN weight storage on analog devices, and propose an approach to jointly optimize model compression and memory resource allocation. We then demonstrate the efficacy of our approach on models trained on MNIST, CIFAR-10 and ImageNet datasets for existing compression techniques. Compared to conventional error-free digital storage, our method reduces the memory footprint by up to one order of magnitude, without significantly compromising the stored model's accuracy., Comment: Published at the ACM Transactions on Embedded Computing Systems (TECS), 2023
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- 2021
13. Electrical Tuning of Phase Change Antennas and Metasurfaces
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Wang, Yifei, Landreman, Patrick, Schoen, David, Okabe, Kye, Marshall, Ann, Celano, Umberto, Wong, H. -S. Philip, Park, Junghyun, and Brongersma, Mark L.
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Physics - Optics ,Physics - Applied Physics - Abstract
The success of semiconductor electronics is built on the creation of compact, low-power switching elements that offer routing, logic, and memory functions. The availability of nanoscale optical switches could have a similarly transformative impact on the development of dynamic and programmable metasurfaces, optical neural networks, and quantum information processing. Phase change materials are uniquely suited to enable their creation as they offer high-speed electrical switching between amorphous and crystalline states with notably different optical properties. Their high refractive index has also been harnessed to fashion them into compact optical antennas. Here, we take the next important step by realizing electrically-switchable phase change antennas and metasurfaces that offer strong, reversible, non-volatile, multi-phase switching and spectral tuning of light scattering in the visible and near-infrared spectral ranges. Their successful implementation relies on a careful joint thermal and optical optimization of the antenna elements that comprise an Ag strip that simultaneously serves as a plasmonic resonator and a miniature heating stage., Comment: 14 pages, 4 figures
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- 2020
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14. Nanotechnology-inspired Information Processing Systems of the Future
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Bryant, Randy, Hill, Mark, Kazior, Tom, Lee, Daniel, Liu, Jie, Nahrstedt, Klara, Narayanan, Vijay, Rabaey, Jan, Siegelmann, Hava, Shanbhag, Naresh, Verma, Naveen, and Wong, H. -S. Philip
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Computer Science - Computers and Society ,Computer Science - Emerging Technologies - Abstract
Nanoscale semiconductor technology has been a key enabler of the computing revolution. It has done so via advances in new materials and manufacturing processes that resulted in the size of the basic building block of computing systems - the logic switch and memory devices - being reduced into the nanoscale regime. Nanotechnology has provided increased computing functionality per unit volume, energy, and cost. In order for computing systems to continue to deliver substantial benefits for the foreseeable future to society at large, it is critical that the very notion of computing be examined in the light of nanoscale realities. In particular, one needs to ask what it means to compute when the very building block - the logic switch - no longer exhibits the level of determinism required by the von Neumann architecture. There needs to be a sustained and heavy investment in a nation-wide Vertically Integrated Semiconductor Ecosystem (VISE). VISE is a program in which research and development is conducted seamlessly across the entire compute stack - from applications, systems and algorithms, architectures, circuits and nanodevices, and materials. A nation-wide VISE provides clear strategic advantages in ensuring the US's global superiority in semiconductors. First, a VISE provides the highest quality seed-corn for nurturing transformative ideas that are critically needed today in order for nanotechnology-inspired computing to flourish. It does so by dramatically opening up new areas of semiconductor research that are inspired and driven by new application needs. Second, a VISE creates a very high barrier to entry from foreign competitors because it is extremely hard to establish, and even harder to duplicate., Comment: A Computing Community Consortium (CCC) workshop report, 18 pages
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- 2020
15. A disposable reader-sensor solution for wireless temperature logging
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Kananian, Siavash, Rho, Jihun, Chen, Cheng, Mirjalili, Shahab, Daus, Alwin, Kim, Min-gu, Niu, Simiao, Pop, Eric, Wong, H.-S. Philip, Bao, Zhenan, Mani, Ali, and Poon, Ada S.Y.
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- 2023
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16. Localized Triggering of the Insulator-Metal Transition in VO2 using a Single Carbon Nanotube
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Bohaichuk, Stephanie M., Rojo, Miguel Muñoz, Pitner, Gregory, McClellan, Connor J., Lian, Feifei, Li, Jason, Jeong, Jaewoo, Samant, Mahesh G., Parkin, Stuart S. P., Wong, H. -S. Philip, and Pop, Eric
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Condensed Matter - Materials Science ,Condensed Matter - Mesoscale and Nanoscale Physics - Abstract
Vanadium dioxide (VO2) has been widely studied for its rich physics and potential applications, undergoing a prominent insulator-metal transition (IMT) near room temperature. The transition mechanism remains highly debated, and little is known about the IMT at nanoscale dimensions. To shed light on this problem, here we use ~1 nm wide carbon nanotube (CNT) heaters to trigger the IMT in VO2. Single metallic CNTs switch the adjacent VO2 at less than half the voltage and power required by control devices without a CNT, with switching power as low as ~85 ${\mu}W$ at 300 nm device lengths. We also obtain potential and temperature maps of devices during operation using Kelvin Probe Microscopy (KPM) and Scanning Thermal Microscopy (SThM). Comparing these with three-dimensional electrothermal simulations, we find that the local heating of the VO2 by the CNT play a key role in the IMT. These results demonstrate the ability to trigger IMT in VO2 using nanoscale heaters, and highlight the significance of thermal engineering to improve device behaviour.
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- 2019
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17. Fast Spiking of a Mott VO2-Carbon Nanotube Composite Device
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Bohaichuk, Stephanie M., Kumar, Suhas, Pitner, Greg, McClellan, Connor J., Jeong, Jaewoo, Samant, Mahesh G., Wong, H-. S. Philip, Parkin, Stuart S. P., Williams, R. Stanley, and Pop, Eric
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Physics - Applied Physics ,Condensed Matter - Mesoscale and Nanoscale Physics - Abstract
The recent surge of interest in brain-inspired computing and power-efficient electronics has dramatically bolstered development of computation and communication using neuron-like spiking signals. Devices that can produce rapid and energy-efficient spiking could significantly advance these applications. Here we demonstrate DC-current or voltage-driven periodic spiking with sub-20 ns pulse widths from a single device composed of a thin VO2 film with a metallic carbon nanotube as a nanoscale heater. Compared with VO2-only devices, adding the nanotube heater dramatically decreases the transient duration and pulse energy, and increases the spiking frequency, by up to three orders of magnitude. This is caused by heating and cooling of the VO2 across its insulator-metal transition being localized to a nanoscale conduction channel in an otherwise bulk medium. This result provides an important component of energy-efficient neuromorphic computing systems, and a lithography-free technique for power-scaling of electronic devices that operate via bulk mechanisms.
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- 2019
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18. Engineering Thermal and Electrical Interface Properties of Phase Change Memory with Monolayer MoS2
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Neumann, Christopher M., Okabe, Kye L., Yalon, Eilam, Grady, Ryan W., Wong, H. -S. Philip, and Pop, Eric
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Physics - Applied Physics ,Condensed Matter - Materials Science - Abstract
Phase change memory (PCM) is an emerging data storage technology, however its programming is thermal in nature and typically not energy-efficient. Here we reduce the switching power of PCM through the combined approaches of filamentary contacts and thermal confinement. The filamentary contact is formed through an oxidized TiN layer on the bottom electrode, and thermal confinement is achieved using a monolayer semiconductor interface, three-atom thick MoS2. The former reduces the switching volume of the phase change material and yields a 70% reduction in reset current versus typical 150 nm diameter mushroom cells. The enhanced thermal confinement achieved with the ultra-thin (~6 {\AA}) MoS2 yields an additional 30% reduction in switching current and power. We also use detailed simulations to show that further tailoring the electrical and thermal interfaces of such PCM cells toward their fundamental limits could lead up to a six-fold benefit in power efficiency.
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- 2019
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19. Self-assembly for electronics
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Kagan, Cherie R, Hyeon, Taeghwan, Kim, Dae-Hyeong, Ruiz, Ricardo, Tung, Maryann C, and Wong, H-S Philip
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Macromolecular and Materials Chemistry ,Materials Engineering ,Mechanical Engineering ,Applied Physics - Abstract
Self-Assembly, a process in which molecules, polymers, and particles are driven by local interactions to organize into patterns and functional structures, is being exploited in advancing silicon electronics and in emerging, unconventional electronics. Silicon electronics has relied on lithographic patterning of polymer resists at progressively smaller lengths to scale down device dimensions. Yet, this has become increasingly difficult and costly. Assembly of block copolymers and colloidal nanoparticles allows resolution enhancement and the definition of essential shapes to pattern circuits and memory devices. As we look to a future in which electronics are integrated at large numbers and in new forms for the Internet of Things and wearable and implantable technologies, we also explore a broader material set. Semiconductor nanoparticles and biomolecules are prized for their size-, shape-, and composition-dependent properties and for their solution-based assembly and integration into devices that are enabling unconventional manufacturing and new device functions.
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- 2020
20. Hyperdimensional Computing Nanosystem
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Rahimi, Abbas, Wu, Tony F., Li, Haitong, Rabaey, Jan M., Wong, H. -S. Philip, Shulaker, Max M., and Mitra, Subhasish
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Computer Science - Emerging Technologies ,Computer Science - Hardware Architecture ,Computer Science - Machine Learning - Abstract
One viable solution for continuous reduction in energy-per-operation is to rethink functionality to cope with uncertainty by adopting computational approaches that are inherently robust to uncertainty. It requires a novel look at data representations, associated operations, and circuits, and at materials and substrates that enable them. 3D integrated nanotechnologies combined with novel brain-inspired computational paradigms that support fast learning and fault tolerance could lead the way. Recognizing the very size of the brain's circuits, hyperdimensional (HD) computing can model neural activity patterns with points in a HD space, that is, with hypervectors as large randomly generated patterns. At its very core, HD computing is about manipulating and comparing these patterns inside memory. Emerging nanotechnologies such as carbon nanotube field effect transistors (CNFETs) and resistive RAM (RRAM), and their monolithic 3D integration offer opportunities for hardware implementations of HD computing through tight integration of logic and memory, energy-efficient computation, and unique device characteristics. We experimentally demonstrate and characterize an end-to-end HD computing nanosystem built using monolithic 3D integration of CNFETs and RRAM. With our nanosystem, we experimentally demonstrate classification of 21 languages with measured accuracy of up to 98% on >20,000 sentences (6.4 million characters), training using one text sample (~100,000 characters) per language, and resilient operation (98% accuracy) despite 78% hardware errors in HD representation (outputs stuck at 0 or 1). By exploiting the unique properties of the underlying nanotechnologies, we show that HD computing, when implemented with monolithic 3D integration, can be up to 420X more energy-efficient while using 25X less area compared to traditional silicon CMOS implementations., Comment: 22 pages, 8 figures
- Published
- 2018
21. Resistive Random Access Memory (RRAM) Technology: From Material, Device, Selector, 3D Integration to Bottom-Up Fabrication
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Chen, Hong-Yu, Brivio, Stefano, Chang, Che-Chia, Frascaroli, Jacopo, Hou, Tuo-Hung, Hudec, Boris, Liu, Ming, Lv, Hangbing, Molas, Gabriel, Sohn, Joon, Spiga, Sabina, Teja, V. Mani, Vianello, Elisa, Wong, H.-S. Philip, Tuller, Harry L., Series Editor, Rupp, Jennifer, editor, Ielmini, Daniele, editor, and Valov, Ilia, editor
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- 2022
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22. Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework
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Sun, Xiaoyu, primary, Peng, Xiaochen, additional, Zhang, Sai, additional, Gomez, Jorge, additional, Khwa, Win-San, additional, Sarwar, Syed, additional, Li, Ziyun, additional, Cao, Weidong, additional, Wang, Zhao, additional, Liu, Chiao, additional, Chang, Meng-Fan, additional, Salvo, Barbara, additional, Akarvardar, Kerem, additional, and Wong, H.-S. Philip, additional
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- 2024
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23. Gate Quantum Capacitance Effects in Nanoscale Transistors
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Desai, Sujay B, Fahad, Hossain M, Lundberg, Theodor, Pitner, Gregory, Kim, Hyungjin, Chrzan, Daryl, Wong, H-S Philip, and Javey, Ali
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Quantum Physics ,Engineering ,Physical Sciences ,Nanotechnology ,Condensed Matter Physics ,Gate quantum capacitance ,limited density of states ,low-dimensional gate ,carbon nanotube gate ,gate charge limited MOSFET ,gate starvation ,CNT-gated SOI MOSFET ,Nanoscience & Nanotechnology - Abstract
As the physical dimensions of a transistor gate continue to shrink to a few atoms, performance can be increasingly determined by the limited electronic density of states (DOS) in the gate and the gate quantum capacitance (CQ). We demonstrate the impact of gate CQ and the dimensionality of the gate electrode on the performance of nanoscale transistors through analytical electrostatics modeling. For low-dimensional gates, the gate charge can limit the channel charge, and the transfer characteristics of the device become dependent on the gate DOS. We experimentally observe for the first time, room-temperature gate quantization features in the transfer characteristics of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) channel transistors; features which can be attributed to the Van Hove singularities in the one-dimensional DOS of the CNT gate. In addition to being an important aspect of future transistor design, potential applications of this phenomenon include multilevel transistors with suitable transfer characteristics obtained via engineered gate DOS.
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- 2019
24. Opportunities for Analog Coding in Emerging Memory Systems
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Engel, Jesse H., Eryilmaz, S. Burc, Kim, SangBum, BrightSky, Matthew, Lam, Chung, Lung, Hsiang-Lan, Olshausen, Bruno A., and Wong, H. -S. Philip
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Computer Science - Information Theory - Abstract
The exponential growth in data generation and large-scale data analysis creates an unprecedented need for inexpensive, low-latency, and high-density information storage. This need has motivated significant research into multi-level memory systems that can store multiple bits of information per device. Although both the memory state of these devices and much of the data they store are intrinsically analog-valued, both are quantized for use with digital systems and discrete error correcting codes. Using phase change memory as a prototypical multi-level storage technology, we herein demonstrate that analog-valued devices can achieve higher capacities when paired with analog codes. Further, we find that storing analog signals directly through joint-coding can achieve low distortion with reduced coding complexity. By jointly optimizing for signal statistics, device statistics, and a distortion metric, finite-length analog encodings can perform comparable to digital systems with asymptotically infinite large encodings. These results show that end-to-end analog memory systems have not only the potential to reach higher storage capacities than discrete systems, but also to significantly lower coding complexity, leading to faster and more energy efficient storage.
- Published
- 2017
25. Beyond-Silicon Devices: Considerations for Circuits and Architectures
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Hills, Gage, Wong, H.-S. Philip, Mitra, Subhasish, Topaloglu, Rasit O., editor, and Wong, H.-S. Philip, editor
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- 2019
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26. Device Engineering and Benefit Maximization for Advanced Cryo-CMOS
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Chiang, Hung-Li, primary, Wu, Jui-Jen, additional, Liao, Pei-Jun, additional, Chen, Tzu-Chiang, additional, Chang, Chih-Sheng, additional, Bao, Xinyu, additional, Cai, Jin, additional, Chang, Marvin F., additional, Chuang, Harry, additional, Diaz, Carlos H., additional, Wong, H.-S. Philip, additional, Passlack, Matthias, additional, and Radu, Iuliana, additional
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- 2024
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27. Heterogeneous 3D Nano-systems: The N3XT Approach?
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Rich, Dennis, Bartolo, Andrew, Gilardo, Carlo, Le, Binh, Li, Haitong, Park, Rebecca, Radway, Robert M., Sabry Aly, Mohamed M., Wong, H.-S. Philip, Mitra, Subhasish, Elitzur, Avshalom C., Series Editor, Merali, Zeeya, Series Editor, Padmanabhan, Thanu, Series Editor, Schlosshauer, Maximilian, Series Editor, Silverman, Mark P., Series Editor, Tuszynski, Jack A., Series Editor, Vaas, Rüdiger, Series Editor, Murmann, Boris, editor, and Hoefflinger, Bernd, editor
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- 2020
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28. Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses
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Eryilmaz, S. Burc, Neftci, Emre, Joshi, Siddharth, Kim, SangBum, BrightSky, Matthew, Lung, Hsiang-Lan, Lam, Chung, Cauwenberghs, Gert, and Wong, H. -S. Philip
- Subjects
Computer Science - Neural and Evolutionary Computing ,Computer Science - Distributed, Parallel, and Cluster Computing ,Computer Science - Emerging Technologies - Abstract
Current large scale implementations of deep learning and data mining require thousands of processors, massive amounts of off-chip memory, and consume gigajoules of energy. Emerging memory technologies such as nanoscale two-terminal resistive switching memory devices offer a compact, scalable and low power alternative that permits on-chip co-located processing and memory in fine-grain distributed parallel architecture. Here we report first use of resistive switching memory devices for implementing and training a Restricted Boltzmann Machine (RBM), a generative probabilistic graphical model as a key component for unsupervised learning in deep networks. We experimentally demonstrate a 45-synapse RBM realized with 90 resistive switching phase change memory (PCM) elements trained with a bio-inspired variant of the Contrastive Divergence (CD) algorithm, implementing Hebbian and anti-Hebbian weight updates. The resistive PCM devices show a two-fold to ten-fold reduction in error rate in a missing pixel pattern completion task trained over 30 epochs, compared to untrained case. Measured programming energy consumption is 6.1 nJ per epoch with the resistive switching PCM devices, a factor of ~150 times lower than conventional processor-memory systems. We analyze and discuss the dependence of learning performance on cycle-to-cycle variations as well as number of gradual levels in the PCM analog memory devices., Comment: Accepted for publication in IEEE Transactions on Electron Devices. This version is the submitted version
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- 2016
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29. High Current Density and Low Thermal Conductivity of Atomically Thin Semimetallic WTe2
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Mleczko, Michal J., Runjie, Xu, Okabe, Kye, Kuo, Hsueh-Hui, Fisher, Ian R., Wong, H. -S. Philip, Nishi, Yoshio, and Pop, Eric
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Condensed Matter - Materials Science ,Condensed Matter - Mesoscale and Nanoscale Physics - Abstract
Two-dimensional (2D) semimetals beyond graphene have been relatively unexplored in the atomically-thin limit. Here we introduce a facile growth mechanism for semimetallic WTe2 crystals, then fabricate few-layer test structures while carefully avoiding degradation from exposure to air. Low-field electrical measurements of 80 nm to 2 um long devices allow us to separate intrinsic and contact resistance, revealing metallic response in the thinnest encapsulated and stable WTe2 devices studied to date (3 to 20 layers thick). High-field electrical measurements and electro-thermal modeling demonstrate that ultra-thin WTe2 can carry remarkably high current density (approaching 50 MA/cm2, higher than most common interconnect metals) despite a very low thermal conductivity (of the order ~3 W/m/K). These results suggest several pathways for air-stable technological viability of this layered semimetal.
- Published
- 2016
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30. Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays
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Li, Haitong, Huang, Peng, Gao, Bin, Liu, Xiaoyan, Kang, Jinfeng, and Wong, H. -S. Philip
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Computer Science - Emerging Technologies - Abstract
Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With Monte Carlo SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependency on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random-access simulations indicate that data sparsity statistically benefits write functionality and energy consumption. Finally, we show that a pseudo-sub-array topology with uniformly distributed pre-forming cells in the pristine high resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance., Comment: Accepted by IEEE Transactions on Electron Devices
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- 2016
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31. Picosecond electric-field-induced threshold switching in phase-change materials
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Zalden, Peter, Shu, Michael J., Chen, Frank, Wu, Xiaoxi, Zhu, Yi, Wen, Haidan, Johnston, Scott, Shen, Zhi-Xun, Landreman, Patrick, Brongersma, Mark, Fong, Scott W., Wong, H. -S. Philip, Sher, Meng-Ju, Jost, Peter, Kaes, Matthias, Salinga, Martin, von Hoegen, Alexander, Wuttig, Matthias, and Lindenberg, Aaron
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Condensed Matter - Materials Science - Abstract
Many chalcogenide glasses undergo a breakdown in electronic resistance above a critical field strength. Known as threshold switching, this mechanism enables field-induced crystallization in emerging phase-change memory. Purely electronic as well as crystal nucleation assisted models have been employed to explain the electronic breakdown. Here, picosecond electric pulses are used to excite amorphous Ag$_4$In$_3$Sb$_{67}$Te$_{26}$. Field-dependent reversible changes in conductivity and pulse-driven crystallization are observed. The present results show that threshold switching can take place within the electric pulse on sub-picosecond time-scales - faster than crystals can nucleate. This supports purely electronic models of threshold switching and reveals potential applications as an ultrafast electronic switch., Comment: 6 pages manuscript with 3 figures and 8 pages supplementary material
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- 2016
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32. Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures
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Eryilmaz, Sukru Burc, Kuzum, Duygu, Yu, Shimeng, and Wong, H. -S. Philip
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Computer Science - Neural and Evolutionary Computing ,Computer Science - Artificial Intelligence - Abstract
This paper gives an overview of recent progress in the brain inspired computing field with a focus on implementation using emerging memories as electronic synapses. Design considerations and challenges such as requirements and design targets on multilevel states, device variability, programming energy, array-level connectivity, fan-in/fanout, wire energy, and IR drop are presented. Wires are increasingly important in design decisions, especially for large systems, and cycle-to-cycle variations have large impact on learning performance., Comment: 4 pages, In Electron Devices Meeting (IEDM), 2015 IEEE International (pp. 4.1). IEEE. Original paper can be found here: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7409622. Abstract can be found here: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7409622&refinements%3D4224410500%26filter%3DAND%28p_IS_Number%3A7409598%29
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- 2015
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33. Electrical tuning of phase-change antennas and metasurfaces
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Wang, Yifei, Landreman, Patrick, Schoen, David, Okabe, Kye, Marshall, Ann, Celano, Umberto, Wong, H.-S. Philip, Park, Junghyun, and Brongersma, Mark L.
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- 2021
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34. Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations
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Hills, Gage, Zhang, Jie, Shulaker, Max Marcel, Wei, Hai, Lee, Chi-Shuen, Balasingam, Arjun, Wong, H. -S. Philip, and Mitra, Subhasish
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Computer Science - Emerging Technologies - Abstract
Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100x faster than existing approaches, and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with less than 5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints.
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- 2015
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35. TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
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Wu, Tony F., Ganesan, Karthik, Hu, Yunqing Alexander, Wong, H. -S. Philip, Wong, Simon, and Mitra, Subhasish
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Computer Science - Hardware Architecture ,Computer Science - Cryptography and Security - Abstract
There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both ASICs and FPGAs. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1. The area and power costs of our approach can range between 7.4-165% and 0.07-60%, respectively, depending on the design and the attacks targeted; 2. The speed impact can be minimal (close to 0%); 3. Our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4. Our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse-engineering). 5. Our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly., Comment: 17 pages, 23 figures. Extended version of paper to appear in IEEE Trans. on CAD
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- 2015
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36. A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime-Part I Intrinsic Elements
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Lee, Chi-Shuen, Pop, Eric, Franklin, Aaron D., Haensch, Wilfried, and Wong, H. -S. Philip
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Condensed Matter - Mesoscale and Nanoscale Physics - Abstract
We presents a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) based on the virtual-source (VS) approach, describing the intrinsic current-voltage and charge-voltage characteristics. The features of the model include: (i) carrier VS velocity extracted from experimental devices with gate lengths down to 15 nm; (ii) carrier effective mobility and velocity depending on the CNT diameter; (iii) short channel effect such as inverse subthreshold slope degradation and drain-induced barrier lowering depending on the device dimensions; (iv) small-signal capacitances including the CNT quantum capacitance effect to account for the decreasing gate capacitance at high gate bias. The CNFET model captures dimensional scaling effects and is suitable for technology benchmarking and performance projection at the sub-10-nm technology nodes., Comment: 8 pages, 10 figures, will be submitted to IEEE transactions on electron devices
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- 2015
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37. A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime - Part II Extrinsic Elements, Performance Assessment, and Design Optimization
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Lee, Chi-Shuen, Pop, Eric, Franklin, Aaron D., Haensch, Wilfried, and Wong, H. -S. Philip
- Subjects
Condensed Matter - Mesoscale and Nanoscale Physics - Abstract
We present a data-calibrated compact model of carbon nanotube (CNT) field-effect transistors (CNFETs) including contact resistance, direct source-to-drain and band-to-band tunneling currents. The model captures the effects of dimensional scaling and performance degradations due to parasitic effects and is used to study the trade-offs between the drive current and leakage current of CNFETs according to the selection of CNT diameter, CNT density, contact length, and gate length for a target contacted gate pitch. We describe a co-optimization study of CNFET device parameters near the limits of scaling with physical insight, and project the CNFET performance at the 5-nm technology node with an estimated contacted gate pitch of 31 nm. Based on the analysis including parasitic resistance, capacitance, and tunneling leakage current, a CNT density of 180 CNTs/{\mu}m will enable CNFET technology to meet the ITRS target of drive current (1.33 mA/{\mu}m), which is within reach of modern experimental capabilities, Comment: 8 pages, 14 figures, will be submitted to IEEE transactions on electron devices
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- 2015
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38. Metal Oxide Resistive Memory using Graphene Edge Electrode
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Lee, Seunghyun, Sohn, Joon, Jiang, Zizhen, Chen, Hong-Yu, and Wong, H. -S. Philip
- Subjects
Condensed Matter - Mesoscale and Nanoscale Physics - Abstract
The emerging paradigm of abundant-data computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors. Todays computing technology, however, cannot scale to satisfy such big data applications with the required throughput and energy efficiency. The next technology frontier will be monolithically integrated chips with three dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene edge to assemble a resistive memory stacked in a vertical three dimensional structure. We report some of the lowest power and energy consumption among the emerging non-volatile memories due to an extremely thin electrode with unique properties, low programming voltages, and low current. Circuit analysis of the architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices., Comment: 41 pages, 15 figures
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- 2015
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39. Resistive Random Access Memory (RRAM) Technology: From Material, Device, Selector, 3D Integration to Bottom-Up Fabrication
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Chen, Hong-Yu, primary, Brivio, Stefano, additional, Chang, Che-Chia, additional, Frascaroli, Jacopo, additional, Hou, Tuo-Hung, additional, Hudec, Boris, additional, Liu, Ming, additional, Lv, Hangbing, additional, Molas, Gabriel, additional, Sohn, Joon, additional, Spiga, Sabina, additional, Teja, V. Mani, additional, Vianello, Elisa, additional, and Wong, H.-S. Philip, additional
- Published
- 2021
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40. Dimensional Scaling of Ferroelectric Properties of Hafnia-Zirconia Thin Films: Electrode Interface Effects.
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Huang, Fei, Saini, Balreen, Wan, Lei, Lu, Haidong, He, Xiaoqing, Qin, Shengjun, Tsai, Wilman, Gruverman, Alexei, Meng, Andrew C., Wong, H.-S. Philip, McIntyre, Paul C., and Wong, Simon
- Published
- 2024
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41. Design Guidelines for Oxide Semiconductor Gain Cell Memory on a Logic Platform
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Liu, Shuhan, primary, Jana, Koustav, additional, Toprasertpong, Kasidit, additional, Chen, Jian, additional, Liang, Zheng, additional, Jiang, Qi, additional, Wahid, Sumaiya, additional, Qin, Shengjun, additional, Chen, Wei-Chen, additional, Pop, Eric, additional, and Wong, H.-S. Philip, additional
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- 2024
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42. Forming-Free Selectors Based on Te in an Insulating SiO xMatrix
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Datye, Isha M., primary, Vaziri, Sam, additional, Ambrosi, Elia, additional, Khan, Asir Intisar, additional, Kwon, Heungdong, additional, Wu, Cheng-Hsien, additional, Hsu, Chen-Feng, additional, Guy, Jeremy, additional, Lee, Tung-Ying, additional, Wong, H.-S. Philip, additional, and Bao, Xinyu, additional
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- 2024
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43. Illusion of large on-chip memory by networked computing chips for neural network inference
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Radway, Robert M., Bartolo, Andrew, Jolly, Paul C., Khan, Zainab F., Le, Binh Q., Tandon, Pulkit, Wu, Tony F., Xin, Yunfeng, Vianello, Elisa, Vivet, Pascal, Nowak, Etienne, Wong, H.-S. Philip, Aly, Mohamed M. Sabry, Beigne, Edith, Wootters, Mary, and Mitra, Subhasish
- Published
- 2021
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44. MoS2 transistors with 1-nanometer gate lengths
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Desai, Sujay B, Madhvapathy, Surabhi R, Sachid, Angada B, Llinas, Juan Pablo, Wang, Qingxiao, Ahn, Geun Ho, Pitner, Gregory, Kim, Moon J, Bokor, Jeffrey, Hu, Chenming, Wong, H-S Philip, and Javey, Ali
- Subjects
Physical Sciences ,Engineering ,Nanotechnology ,Condensed Matter Physics ,General Science & Technology - Abstract
Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.
- Published
- 2016
45. Barrier Booster for Remote Extension Doping and its DTCO for 1D & 2D FETs
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Gilardi, Carlo, primary, Zeevi, Gilad, additional, Choi, Suhyeong, additional, Su, Sheng-Kai, additional, Hung, Terry Y.T., additional, Li, Shengman, additional, Safron, Nate, additional, Lin, Qing, additional, Srimani, Tathagata, additional, Passlack, Matthias, additional, Pitner, Gregory, additional, Chen, Edward, additional, Radu, Iuliana, additional, Wong, H.-S. Philip, additional, and Mitra, Subhasish, additional
- Published
- 2023
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46. Low N-Type Contact Resistance to Carbon Nanotubes in Highly Scaled Contacts through Dielectric Doping
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Safion, Nathaniel, primary, Chiu, Hsin-Yuan, additional, Chao, Tzu-Ang, additional, Su, Sheng-Kai, additional, Passlack, Matthias, additional, Chiu, Kuang-Hsiang, additional, Chen, Chien-Wei, additional, Kei, Chi-Chung, additional, Chou, Chen-Han, additional, Lee, Tsung-En, additional, Wang, Jer-Fu, additional, Chang, Chih-Sheng, additional, Liew, San-Lin, additional, Hou, Vincent D- H., additional, Wang, Han, additional, Chang, Wen-Hao, additional, Wong, H.-S. Philip, additional, Pitner, Gregory, additional, Chien, Chao-Hsin, additional, and Radu, Iuliana P., additional
- Published
- 2023
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47. Multi-gate FeFET Discriminates Spatiotemporal Pulse Sequences for Dendrocentric Learning
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Chen, Hugo J.-Y., primary, Beauchamp, Matthew, additional, Toprasertpong, Kasidit, additional, Huang, Fei, additional, Le Coeur, Louis, additional, Nemec, Thorgund, additional, Wong, H.-S. Philip, additional, and Boahen, Kwabena, additional
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- 2023
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48. Gain Cell Memory on Logic Platform – Device Guidelines for Oxide Semiconductor Transistor Materials Development
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Liu, Shuhan, primary, Jana, Koustav, additional, Toprasertpong, Kasidit, additional, Chen, Jian, additional, Liang, Zheng, additional, Jiang, Qi, additional, Wahid, Sumaiya, additional, Qin, Shengjun, additional, Chen, Wei-Chen, additional, and Wong, H.-S. Philip, additional
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- 2023
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49. Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel
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Chou, Ang-Sheng, primary, Hsu, Ching-Hao, additional, Lin, Yu-Tung, additional, Arutchelvan, Goutham, additional, Chen, Edward, additional, Hung, Terry Y.T., additional, Hsu, Chen-Feng, additional, Chou, Sui-An, additional, Lee, Tsung-En, additional, Madia, Oreste, additional, Doornbos, Gerben, additional, Su, Yuan-Chun, additional, Azizi, Amin, additional, Sathaiya, D. Mahaveer, additional, Cai, Jin, additional, Wang, Jer-Fu, additional, Chung, Yun-Yan, additional, Wu, Wen-Chia, additional, Neilson, Katie, additional, Yun, Wei-Sheng, additional, Hsu, Yu-Wei, additional, Hsu, Ming-Chun, additional, Hou, Fa-Rong, additional, Shen, Yun-Yang, additional, Chien, Chao-Hsin, additional, Wu, Chung-Cheng, additional, Wu, Jeff, additional, Wong, H.-S. Philip, additional, Chang, Wen-Hao, additional, van Dal, Mark, additional, Cheng, Chao-Ching, additional, Wu, Chih-I, additional, and Radu, Iuliana P., additional
- Published
- 2023
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50. High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies
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Lee, Tsung-En, primary, Chiang, Hung-Li, additional, Chang, Chih-Yu, additional, Su, Yuan-Chun, additional, Chang, Shu-Jui, additional, Wu, Jui-Jen, additional, Lin, Bo-Jiun, additional, Wang, Jer-Fu, additional, Haw, Shu-Chih, additional, Chiu, Shang-Jui, additional, Ching, He-Liang, additional, Lin, Yan-Gu, additional, Yun, Wei-Sheng, additional, Hsu, Chen-Feng, additional, Lee, Hengyuan, additional, Lee, Tung-Ying, additional, Passlack, Matthias, additional, Cheng, Chao-Ching, additional, Chang, Chih-Sheng, additional, Wong, H.-S. Philip, additional, Chang, Wen-Hao, additional, Chang, Meng-Fan, additional, Lin, Yu-Ming, additional, and Radu, Iuliana P., additional
- Published
- 2023
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- View/download PDF
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