303 results on '"Wu, Yung-Chun"'
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2. High-Speed and Low-Power Ferroelectric HfO$_{\text{2}}$/ZrO$_{\text{2}}$ Superlattice FinFET Memory Device Using AlON Interfacial Layer
3. Steep Slope Tunnel FET Simulation
4. Junctionless FET with L g = 10 nm Simulation
5. Inverter and SRAM of FinFET with L g = 15 nm Simulation
6. Extremely Scaled Si and Ge to L g = 3-nm FinFETs and L g = 1-nm Ultra-Thin Body Junctionless FET Simulation
7. 3D FinFET with L g = 15 nm and L g = 10 nm Simulation
8. Gate-All-Around (GAA) NWFET with L g = 10 nm Simulation
9. 2D MOSFET Simulation
10. Introduction of Synopsys Sentaurus TCAD Simulation
11. Study of Ferroelectric HfO2-ZrO2 Superlattice Poly-Si Junctionless Nanosheet Gate-all-around Field-effect-transistor and CMOS Inverter
12. Investigation of HfO2/ZrO2 Superlattice Dielectric and High-k AION Interfacial Layer on Ferroelectric FinFET
13. Green Laser Crystallized Poly-Si Thin-film Transistor and CMOS Inverter using Hfo2-Zro2 Superlattice Gate Insulator and Microwave Annealing for BEOL Applications
14. Vertically Stacked Ge Diamond-shape Nanowires GAAFET with Ferroelectric HZO
15. Effect of fin shape of tapered FinFETs on the device performance in 5-nm node CMOS technology
16. Investigation of inversion, accumulation and junctionless mode bulk Germanium FinFETs
17. High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET
18. SiGe/Si Superlattice Ferroelectric HfZrO2 ΩFET and CMOS Inverter With SSmin,n = 62.4 mV/dec, ION/IOFF > 1.0 × 107, and Voltage Gain = 111.4 V/V
19. 3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET
20. SiGe/Si Superlattice Ferroelectric HfZrO2 ΩFET and CMOS Inverter with SSmin,n = 62.4 mV/dec, ION/IOFF > 1.0 × 107, and Voltage Gain = 111.4 V/V
21. Multilevel Cell Ferroelectric HfZrO FinFET With High Speed and Large Memory Window Using AlON Interfacial Layer
22. 3D TCAD Simulation for CMOS Nanoeletronic Devices
23. Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET)
24. Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application
25. Extremely Scaled Si and Ge to L g = 3-nm FinFETs and L g = 1-nm Ultra-Thin Body Junctionless FET Simulation
26. Introduction of Synopsys Sentaurus TCAD Simulation
27. Steep Slope Tunnel FET Simulation
28. 3D FinFET with L g = 15 nm and L g = 10 nm Simulation
29. Gate-All-Around (GAA) NWFET with L g = 10 nm Simulation
30. 2D MOSFET Simulation
31. Inverter and SRAM of FinFET with L g = 15 nm Simulation
32. Junctionless FET with L g = 10 nm Simulation
33. Collection Efficiency Enhancement of Injected Electrons in Dye- sensitized Solar Cells with a Ti Interfacial Layer and TiCl4Treatment
34. Charge Storage Characteristics of Pi-Gate Poly-Si Nanowires TaN-Al2O3-Si3N4-SiO2-Si Flash Memory
35. Investigation of SiGe/Si Bilayer Inverted-T Channel Gate-all-around Field-effect-transistor with Self-induced Ferroelectric Ge doped HfO2
36. Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
37. Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor
38. A single poly-Si gate-all-around junctionless fin field-effect transistor for use in one-time programming nonvolatile memory
39. Tightly Stacked 3D Diamond-Shaped Ge Nanowire Gate-All-Around FETs With Superior nFET and pFET Performance
40. High Speed and Large Memory Window Ferroelectric HfZrO₂ FinFET for High-Density Nonvolatile Memory
41. Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory
42. Temperature-dependent memory characteristics of silicon–oxide–nitride–oxide–silicon thin-film-transistors
43. Compensation of Voltage Sags and Swells Using Dynamic Voltage Restorer Based on Bi-Directional H-Bridge AC/AC Converter
44. Exploring Carrier Transport Mechanisms of Inversion, Accumulation, and Junctionless Mode of Vertical Stacked Nanosheet Field Effect Transistor for N5 Logic Technology
45. Comprehensive Study of Inversion and Junctionless Ge Nanowire Ferroelectric HfZrO Gate-All-Around FETs Featuring Steep Subthreshold Slope with Transient Negative Capacitance
46. Trench FinFET Nanostructure with Advanced Ferroelectric Nanomaterial HfZrO 2 for Sub-60-mV/Decade Subthreshold Slope for Low Power Application.
47. Application of fluorine doped oxide (SiOF) spacers for improving reliability in low temperature polycrystalline thin film transistors
48. Performance enhancement of excimer laser crystallized poly-Si thin film transistors with fluorine implantation technology
49. A three-in-one converter for regular and emergency lighting applications
50. Self-induced ferroelectric 2-nm-thick Ge-doped HfO2 thin film applied to Ge nanowire ferroelectric gate-all-around field-effect transistor
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