Search

To investigate the factors for recurrence in acute central serous chorioretinopathy (aCSC) for patients who underwent one-third dose verteporfin photodynamic therapy (PDT).A retrospective study was performed in aCSC patients treated with one-third dose PDT and followed up for 36 months. Demographic information and clinical features were compared. A logistic regression model was used to evaluate the associated factor of aCSC recurrence.There were 162 patients with aCSC included in current study. 36-month after one-third dose PDT, good recovery was identified in 131 patients (80.86%), whereas 31 cases (19.14%) developed recurrence. Significant between-group differences were observed in baseline age, the right, left and both eyes, best-corrected visual acuity (BCVA), presenting with pigment epithelium detachment (PED), retinal pigment epithelium (RPE) damage and subfoveal choroidal thickness (SCT) level (P = 0.005, P 0.001, P0.001, P0.001, P = 0.006, and P0.001, respectively). The recurrence of aCSC was associated with presenting with PED (odds ratio = 1.78; 95% CI, 1.45-1.98; P0.001), RPE damage (OR = 1.13; 95%CI: 1.08-1.23; P0.001), baseline BCVA (OR = 0.96; 95%CI: 0.95 - 0.99; P = 0.001), and SCT level (OR = 1.18; 95%CI: 1.02-1.20; P 0.001).In acute CSC after treatment of one-third dose PDT, recurrence is associated with RPE damage, baseline BCVA and SCT level. Our findings will assist clinicians to evaluate aCSC in clinical practice and provide insights into the prevention of recurrence.

Eugenol, as an active compound isolated from Acorus gramineus, has been shown to protect against cerebral ischemia-reperfusion (I/R) injury. Nonetheless, the detailed neuroprotective mechanisms of eugenol in cerebral I/R injury have not been elaborated. In the present study, cerebral I/R injury model was established by middle cerebral artery occlusion (MCAO) in rats. HT22 cells were subjected to oxygen-glucose deprivation/reperfusion (OGD/R) to mimic cerebral I/R injury in vitro. The results showed that eugenol pre-treatment relieved cerebral I/R injury as evidenced by improving neurological deficits and reducing infarct volume. Autophagy was induced by MCAO, which was further promoted by eugenol administration. Moreover, rapamycin, an activator of autophagy, promoted eugenol-induced decreases in neurological score, infarct volume, brain water content, and apoptosis. However, pretreatment with 3-MA, an inhibitor of autophagy, led to the opposite results. Similarly, eugenol pretreatment increased the viability and restrained apoptosis of OGD/R-challenged HT22 cells. OGD/R-induced autophagy was strengthened by eugenol. Mechanically, eugenol promoted autophagy through regulating AMPK/mTOR/P70S6K signaling pathway in vivo and in vitro. In conclusion, pretreatment with eugenol attenuated cerebral I/R injury by inducing autophagy via AMPK/mTOR/P70S6K signaling pathway.

Pancreatic beta-like cells generated from human induced pluripotent stem cells (hiPSCs) or human embryonic stem cells (hESCs) offer an appealing donor tissue source. However, differentiation protocols that mainly use growth factors are costly. Therefore, in this study, we aimed to establish efficient differentiation protocols to change hiPSCs/hESCs to insulin (INS)+ cells using novel small-molecule inducers. We screened small molecules that increased the induction rate of INS+ cells from hESC-derived pancreatic and duodenal homeobox 1 (PDX1)+ pancreatic progenitor cells. The differentiation protocol to generate INS+ cells from hiPSCs/hESCs was optimised using hit compounds, and INS+ cells induced with the compounds were characterised for their in vitro and in vivo functions. The inducing activity of the hit compounds was also examined using mouse embryonic pancreatic tissues in an explant culture system. Finally, RNA sequencing analyses were performed on the INS+ cells to elucidate the mechanisms of action by which the hit compounds induced pancreatic endocrine differentiation. One hit compound, sodium cromoglicate (SCG), was identified out of approximately 1250 small molecules screened. When SCG was combined with a previously described protocol, the induction rate of INS+ cells increased from a mean ± SD of 5.9 ± 1.5% (n = 3) to 16.5 ± 2.1% (n = 3). SCG induced neurogenin 3-positive cells at a mean ± SD of 32.6 ± 4.6% (n = 3) compared with 14.2 ± 3.6% (n = 3) for control treatment without SCG, resulting in an increased generation of endocrine cells including insulin-producing cells. Similar induction by SCG was confirmed using mouse embryonic pancreatic explants. We also confirmed that the mechanisms of action by which SCG induced pancreatic endocrine differentiation included the inhibition of bone morphogenetic protein 4 signalling. SCG improves the generation of pancreatic endocrine cells from multiple hiPSC/hESC lines and mouse embryonic pancreatic explants by facilitating the differentiation of endocrine precursors. This discovery will contribute to elucidating the mechanisms of pancreatic endocrine development and facilitate cost-effective generation of INS+ cells from hiPSCs/hESCs. The RNA sequencing data generated during the current study are available in the Gene Expression Omnibus ( www.ncbi.nlm.nih.gov/geo ) with series accession number GSE89973.

Purpose: To study the safety and efficacy of 1/3-dose verteporfin photodynamic therapy (PDT) for subacute central serous chorioretinopathy (CSC). Methods: In this case series, 59 eyes (59 patients) diagnosed with subacute CSC in Shenyang the 4th hospital from January 2014 to December 2015 were treated with 1/3-dose verteporfin PDT and followed up for at least 1 year. The symptoms and the diagnosed history were more than 3 months but shorter than 6 months. The central foveal thickness (CFT), neuroretinal thickness (NRT), height of subfoveal retinal fluid (SRF), and subfoveal choroidal thickness (SCT) were observed at baseline and after treated at 1, 2, 3, 6 and 12 months with EDI-OCT, Best-corrected visual acuity ( BCVA) was also studied at the same time. Results: After 1, 2, 3 and 6 months of 1/3-dose verteporfin PDT treatment, the BCVA improved significantly (P 0.05). The height of SRF changed significantly. There was no retinal pigment epithelium atrophy and choroidal neovascularization (CNV) in all cases after more than 12 months follow-up. Conclusion: Treatment of 1/3 dose verteporfin PDT could safely and effectively reduce expansion of choroidal vessel and choroidal choriocapillary, promoting absorbance of subretinal fluid for subacute CSC. 1/3-dose verteporfin PDT may be an alternative method to treat the subacute CSC.

The present paper takes the popular language expressions in Chinese relating to the Moe Culture after its introduction from Japanese as the research object, aiming to analyze the important role of phonetic adjustment in enhancing the effect of Moe culture from the perspective of linguistics. It points out that reduplication, fusion and inflexion may enhance the effect of Moe culture through three specific mechanisms. The conclusion of the present study provides an angle and facts for clarifying the contact between Moe Culture and Chinese language under the development of modern society.

In clinical islet transplantation, because the long-term insulin-independence rate is still poor, a method for detailed analysis of the transplanted islets in the liver after transplantation is required. We have established a novel imaging technique suitable for analysis of transplanted islets in liver using an optical projection tomography (OPT) method. A three-dimensional tomographic image of the transplanted islets in liver was reconstructed. The number of islets transplanted and the number of transplanted islets observed using OPT showed good correlation. The OPT method was used to compare the numbers of transplanted islets in mouse syngeneic and allogeneic transplantation models. Blood glucose concentrations of streptozotocin (STZ)-induced diabetic mice transplanted with syngeneic islets remained normoglycemic and the number of transplanted islets was largely preserved 11 days after transplantation. In mice transplanted with allogeneic islets, hyperglycemia recurred from 7 days after transplantation and the number and the volume of transplanted islets was significantly reduced 11 days after transplantation. These results indicate that OPT imaging and analysis may be a useful tool to quantitatively and sterically evaluation of transplanted islets in liver at the cellular level.

Modern embedded processors with dedicated address generation unit support memory accesses through auto-increment/decrement addressing mode. The auto-increment/decrement mode, if properly utilized, can save address arithmetic instructions, reduce static and dynamic memory footprint of the program, and speed up the execution as well. Liao [1995, 1996] categorized this problem as Simple Offset Assignment (SOA) and General Offset Assignment (GOA), which involves storage layout of variables and assignment of address registers, respectively, proposing several heuristic solutions. This article proposes a new direction for investigating the solution space of the problem. The general idea [Zhuang 2003] is to perform simplification of the underlying access graph through coalescence of the memory locations of program variables. A comprehensive framework is proposed including coalescence-based offset assignment and post/pre-optimization. Variables not interfering with others (not simultaneously live at any program point) can be coalesced into the same memory location. Coalescing allows simplifications of the access graph yielding better SOA solutions; it also reduces the address register pressure to such low values that some GOA solutions become optimal. Moreover, it can reduce the memory footprint both statically and at runtime for stack variables. Our second optimization (post/pre-optimization) considers both post- and pre-modification mode for optimizing code across basic blocks, which makes it useful. Making use of both addressing modes further reduces SOA/GOA cost and our post/pre-optimization phase is optimal in selecting post or pre mode after variable offsets have been determined. We have shown the advantages of our framework over previous approaches to capture more opportunities to reduce both stack size and SOA/GOA cost, leading to more speedup.

Many modern embedded processors such as DSPs support partitioned memory banks (also called X--Y memory or dual-bank memory) along with parallel load/store instructions to achieve higher code density and performance. In order to effectively utilize the parallel load/store instructions, the compiler must partition the memory-resident values and assign them to X or Y bank. This paper gives a postregister allocation solution to merge the generated load/store instructions into their parallel counterparts. Simultaneously, our framework performs allocation of values to X or Y memory banks. We first remove as many load/stores and register--register moves as possible through an excellent iterated coalescing based register allocator by Appel and George [1996]. We then attempt to parallelize the generated load/stores using a multipass approach. The basic phase of our approach attempts the merger of load/stores without duplication and web splitting. We model this problem as a graph-coloring problem in which each value is colored as either X or Y. We then construct a motion scheduling graph (MSG), based on the range of motion for each load/store instruction. MSG reflects potential instructions that could be merged. We propose a notion of pseudofixed boundaries so that the load/store movement is less affected by register dependencies. We prove that the coloring problem for MSG is NP-complete and solve it with two different heuristic algorithms with different complexity. We then propose a two-level iterative process to attempt instruction duplication, variable duplication, web splitting, and local conflict elimination to effectively merge the remaining load/stores. Finally, we clean up some multiple-aliased load/stores. To improve the performance, we combine profiling information with each stage coupled with some modifications to the algorithm. We show that our framework results in parallelization of a large number of load/stores without much growth in data and code segments. The average speedup for our optimization pass reaches roughly 13% if no profile information is available and 17% with profile information. The average code and data segment growth is controlled within 13%.

Calling context profiles are used in many inter-procedural code optimizations and in overall program understanding. Unfortunately, the collection of profile information is highly intrusive due to the high frequency of method calls in most applications. Previously proposed calling-context profiling mechanisms consequently suffer from either low accuracy, high overhead, or both. We have developed a new approach for building the calling context tree at runtime, called adaptive bursting . By selectively inhibiting redundant profiling, this approach dramatically reduces overhead while preserving profile accuracy. We first demonstrate the drawbacks of previously proposed calling context profiling mechanisms. We show that a low-overhead solution using sampled stack-walking alone is less than 50% accurate, based on degree of overlap with a complete calling-context tree. We also show that a static bursting approach collects a highly accurate profile, but causes an unacceptable application slowdown. Our adaptive solution achieves 85% degree of overlap and provides an 88% hot-edge coverage when using a 0.1 hot-edge threshold, while dramatically reducing overhead compared to the static bursting approach.

Micro-architecture designers are very cautious about expanding the number of architected registers (also the register field), because increasing the register field adds to the code size, raises I-cache and memory pressure, complicates processor pipeline. Especially for low-end processors, encoding space could be extremely limited due to area and power considerations. On the other hand, the number of architected registers exposed to the compiler could directly affect the effectiveness of compiler analysis and optimization. For high performance computers, register pressure can be higher than the available registers in some regions, e.g. due to optimizations like aggressive function inlining, software pipelining etc. The compiler cannot effectively perform compilation and optimization if only a small number of registers are exposed through the ISA. Therefore, it is crucial that more architected registers are available at the compiler's disposal without expanding the code size significantly.In this paper, we look at a new register encoding scheme called differential encoding that allows more registers to be addressed in the operand field of instructions than the direct encoding currently being used. We show it can be implemented with very low overhead. Based upon differential encoding, we apply it in several ways such that the extra architected registers can benefit the performance. Three schemes are devised to integrate differential encoding with register allocation. We demonstrate that differential register allocation is helpful in improving the performance of both high-end and low-end processors. Moreover, We can combine it with software pipelining to provide more registers and reduce spills.Our results show that differential encoding significantly reduces the number of spills and speeds up program execution. For a low-end configuration, we achieve over 12% speedup while keeping code size almost unaffected. For optimization on loops, it significantly speeds up loops with high register pressure (over 70% speedup).

XOM-based secure processor has recently been introduced as a mechanism to provide copy and tamper resistant execution. XOM provides support for encryption/decryption and integrity checking. However, neither XOM nor any other current approach adequately addresses the problem of information leakage via the address bus. This paper shows that without address bus protection, the XOM model is severely crippled. Two realistic attacks are shown and experiments show that 70% of the code might be cracked and sensitive data might be exposed leading to serious security breaches.Although the problem of address bus leakage has been widely acknowledged both in industry and academia, no practical solution has ever been proposed that can provide an adequate security guarantee. The main reason is that the problem is very difficult to solve in practice due to severe performance degradation which accompanies most of the solutions. This paper presents an infrastructure called HIDE (Hardware-support for leakage-Immune Dynamic Execution) which provides a solution consisting of chunk-level protection with hardware support and a flexible interface which can be orchestrated through the proposed compiler optimization and user specifications that allow utilizing underlying hardware solution more efficiently to provide better security guarantees.Our results show that protecting both data and code with a high level of security guarantee is possible with negligible performance penalty (1.3% slowdown).