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This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

This brief presents an ultra-low-power (ULP) current reference circuit based on $V_{th}$ (threshold voltage), which consumes pico-watt of power under 0.5V supply voltage. Compared to traditional current references based on threshold voltage, this design uses no amplifier, thus friendly scaling and simple structure are achieved simultaneously. In order to save area, the huge resistor is replaced by a gate-leakage MOS transistor. The proposed circuit is designed in a 40nm CMOS process. The minimum supply voltage is 0.5V. Post simulation results show that the power consumption is only 8.2pW at 0.5V $V_{DD}$ at room temperature. According to our knowledge, this is the smallest power consumption compared to prior works, thanks to its simple structure. Under process + mismatch Monte-Carlo simulations, the temperature coefficient after trimming is 18.6ppm/°C over 0°C to 85°C. The core area is only 0.00025mm2 in layout. Apart from the 40nm process, this circuit is also designed in a 130nm process to demonstrate the robustness under different processes.

A high-speed comparator constituted by a backgate-input latch and a pre-amplifier is proposed in this paper. Instead of using extra input transistors as in a classic StrongARM latch, the back-gate-input technique proposed in this paper obviates the need for extra input transistors in the latch stage, thus greatly reducing the parasitic capacitance and improving the comparator speed. Unlike the StrongARM latch where the amplification phase begins only after the CLK rises, the amplification phase in this paper begins before the CLK rises and replaces the reset phase, further improving the comparator speed. The pre-amplifier provides a gain of 22-dB, in order to suppress the input-referred noise and offset of the comparator. Designed in the same 22nm Silicon-on-Insulator (SOI) CMOS process for the proposed comparator and the conventional comparators, post-layout simulation results show that the performance in speed and input-referred noise are improved by 22% and 43%, respectively.

This paper presents a bootstrapped switch with an accelerated gate-voltage rising speed and a reduced on- resistance for high-speed ADCs. Compared to the classic bootstrapped switch, this design accelerates the rising speed of gate voltage through four novel techniques. First, an extra NMOS transistor is added to pull up the gate voltage by injecting extra charges into the gate node. Second, the parasitic capacitance at the gate node is reduced by simplifying the circuit structure, leading to a faster speed. Third, transmission gates are used to reduce the two delays to one delay. Fourth, the voltage stored on the capacitor is increased to slightly larger than V DD , which leads to a faster gate-voltage rising speed as well as a larger value of gate voltage (about V n +1.05 V DD ). The larger gate voltage also helps reduce the on-resistance of the bootstrapped switch, which is helpful for the high-speed sampling of ADCs. In a 40 nm CMOS process, post-layout simulation results show that the rising speed of gate voltage is increased by 3.3 times compared to the classic thin-oxide bootstrapped switch circuit. And the on-resistance of the bootstrapped switch is reduced by 2.2 times compared to the classic structure, due to the larger gate voltage value.

This paper presents a fully differential 12-bit SAR ADC with a novel capacitor mismatch calibration. The calibration calculates the capacitor mismatch via the metastability of the comparator and statistical method. A novel metastability detection circuit is designed to ensure the detection accuracy and avoid the “fake metastability” problem. Post-simulation shows that the ENOB is improved by 1.52 bits to achieve 11.71 bits at 130MSps sampling rate using the proposed calibration algorithm.

This paper proposes a novel high-precision ADC digital calibration algorithm based on neural network (NN). The algorithm is to suppress the harmonic distortion caused by the non-ideal factors in ADC. As a result, regardless of the non-ideal types, it can be universally used as a back-end calibration black box in various ADC structures. A 14-bit ADC with trained NN reaches more than 12.3-bit of ENOB in behavioral simulation. We also applied the NN to a practical 12-bit sigma-delta ADC and achieved a significant improvement of more than 1-bit of ENOB.

A 14bits 1GSps Pipelined-SAR (P-SAR) ADC design is presented in this paper. We apply 4 sub-stages with each stage using a 4-bit sub SAR ADC to reach an optimized overall performance. A new dynamic amplifier is proposed and used as the residue amplifier (RA), which improves the linearity and reduce the power largely. The multi-comparator structure is used in sub SAR ADC, which significantly reduces the comparator's reset time and hence increase the conversion speed a lot. For each single comparator, a two-stage structure is designed to effectively reduce the kickback noise. Besides, since it is extremely difficult to obtain precise interstage gain with open-loop dynamic amplifier, we propose a novel digital background calibration technique based on comparator metastability to compensate the interstage gain error and capacitor mismatches. This P-SAR ADC is designed in a 22nm FD-SOI process. The simulation results show that our ADC achieves an SNDR of 69dB and an SFDR of 85dB respectively with the input signal frequency of 100MHz at a sampling rate of 1GS/s. The core ADC consumes 109mW (excluding the reference generator).

This paper presents a novel sub-nW voltage reference circuit for ultra-low-power systems. It saves power by using a 2-transistor (2-T) structure that produces a stable voltage based on transistor threshold voltage difference. A well-controlled bias current is produced by a novel current generator that reduces the temperature coefficient (TC). Fabricated in 180nm CMOS process, this reference circuit consumes only 0.5nW power. It achieves an average TC of 29ppm/°C and a line sensitivity (LS) of 0.18%/V, measured across 22 chips.

This paper proposes a novel comparator offset calibration technique for SAR ADCs. We realize the calibration in CDAC instead of the comparator circuit, so that the power consumption, area and circuit complexity barely increase, which is a big advantage compared to traditional ones. A 10-bit 100Msps SAR ADC applying our offset calibration is designed in a 55nm CMOS process. The post simulation results show that the ENOB achieves 9.5 bits and consumes a power of 4.4mW at the sampling rate of 100MHz.

This paper presents a novel high accuracy background calibration design for pipelined ADC. Pseudorandom (PN) sequences are used for gain error calibration but also limit the calibration accuracy because of the inherent quantization noise. So we add redundant stages and derive new algorithm to reduce the impact of quantization noise and improve the accuracy of gain error calibration. A 12-Bit 1Gsps RF sampling pipelined ADC using our proposed digital calibration has been designed. Both behavioral and post simulation indicates the proposed calibration works effectively, where the post simulation results show the ADC reaches an SNDR of 66.6 dB (ENOB=9.72-Bit) at 1GSps sampling rate after the calibration.

We have been developing a large-scale reconfigurable data path (LSRDP) based on single-flux-quantum (SFQ) circuit technology for high-performance computing systems. In the SFQ LSRDP, a large number of SFQ floating-point adders (FPAs) and floating-point multipliers (FPMs) are directly connected to each other through routing networks to reduce a memory access rate. In this paper, we show our recent results about the SFQ FPAs and FPMs. Utilization of the National Institute of Advanced Industrial Science and Technology's 10-kA/cm 2 Nb process makes it possible to accelerate the clock frequency to more than 50 GHz. We successfully demonstrated the high-speed operation of single- precision FPAs and FPMs, whose clock frequency is beyond 50 GHz, by on-chip high-speed tests. We estimate the performance and energy efficiency of SFQ FPAs and FPMs based on the designed circuits.

The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of “1.” The main contribution of this paper is to demonstrate a single-flux-quantum (SFQ)-based hardware algorithm that performs an exhaustive search to verify the Collatz conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator, and a central processor. This design can perform at up to a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW in simulation, based on the AIST 10 kA/cm 2 advanced Nb process. An LR-biasing approach further reduces the power consumption, whereas the computing speed can be accelerated by a factor of 20 when accelerating approaches are adopted. The assessments show that our design can process 2 × 10 7 numbers every second with an energy efficiency of about 5 × 10 10 numbers per Joule.

With many advanced superconductive integrated circuit fabrication processes now moving to multiple ground/shield layers and buried signal lines, and gate dimensions shrinking, the inductance of stacked vias becomes significant. Analytical and two-dimensional inductance calculation methods cannot account for stacked via inductance. Here we show experimental test structures devised to verify the calculated inductance of stacked vias with the three-dimensional utility InductEx. The structures are manufactured in the AIST 9-layer ADP2 process, and are measured through SQUID modulation. We discuss the effects of the absence of ground sleeves around the vias on return current paths and inductance, as well as the coupling between stacked vias in close proximity, and present experimental results. Finally we examine the reliability of calculations with InductEx for such via structures.

A systematic design methodology, composed of a BW/gain model and an offset modeling mechanism, is proposed for high-speed interpolation/averaging ADCs. The methodology is able to conduct a systematic analysis and reaches an optimized ADC design with given specs (i.e., resolution, speed, input range, power, input CM, etc.). It shows significant advantage over the traditional trial-and-error ADC design approach with respect to performance, design efficiency and reliability in nano-meter technologies. Using our methodology, a 4-bit 5GSps prototype ADC is designed and fabricated in a 65nm CMOS technology. The measurement results show that our ADC has indeed achieved an outstanding overall performance compared to the reported state-of-the art ADCs.

The AIST advanced process (ADP2), with 9 Nb layers and 1 μm minimum Josephson junction size is currently the most complex low-Tc superconductive integrated circuit fabrication process in operation. With planarization for all layers below the main ground plane, and conductors that may traverse several layers, modeling inductance for numerical calculation requires special attention to the capabilities of the extraction tool. We present specific improvements made to InductEx to model the ADP process, including support for selective layer planarization, multiple ground planes and conductors below a ground plane. We discuss calibration of extracted values to experimental results, and show results for pulse transfer cells with inductive coupling and isolated ground planes.

We have been developing Josephson/CMOS hybrid memories, where decoders and memory cell arrays are composed of CMOS devices and bit-line current sensors are made by Josephson circuits. In our previous study we reported a fully functional 64-kb CMOS static RAM for the hybrid memory, which includes CMOS differential amplifiers with 40-mV voltage inputs. In this paper we demonstrate a fully functional 64-kb Josephson/CMOS hybrid memory, which is composed SFQ input/output circuits using the AIST Nb standard process and a CMOS static RAM using the Rohm 180 nm CMOS process. All input data, are inputs to the hybrid memory as SFQ signals in the system. The total access time was measured to be about 1.69 ns.