67 results on '"Xu, Zule"'
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2. 23.5 A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End
3. A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering
4. A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications
5. Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation
6. A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration
7. An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering
8. A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter and −240-dB FOMjitter
9. A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal
10. Analysis and simulation of MOSFET-based gate-voltage-independent capacitor
11. A fractional‐N MASH2‐k FDC phase‐locked loop architecture enabling higher‐order quantisation noise shaping
12. An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC
13. A 0.79–1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving −232.8-dB FoMref
14. A 24-MHz 13-µW CTGS Class-C Complementary Colpitts Crystal Oscillator with On-Chip Background Temperature Compensation
15. CTGS圧電単結晶振動子を用いた世界最小電力基準クロック発生回路
16. A 24-MHz 13-μW CTGS Class-C Complementary Colpitts Crystal Oscillator with On-Chip Background Temperature Compensation
17. Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector
18. A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with −80-dBc Reference Spur
19. A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving –66dBc Worst-Case In-Band Fractional Spur
20. A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -65 dBc In-Band Fractional Spur
21. Ultralow-Power Class-C Complementary Colpitts Crystal Oscillator
22. A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS
23. An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration
24. A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool
25. Picosecond Resolution Time-to-Digital Converter Using Gm-C Integrator and SAR-ADC
26. A 2GHz 3.1mW Type-I Digital Ring-Based PLL
27. A Low-Power Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Charge-Pump and SAR ADC
28. A 74.5 dB SNDR 1 MHz Bandwidth 1.17 mW Delta-Sigma Time to Digital Converter Using Charge-Pump and SAR ADC
29. Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error
30. High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator
31. Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs
32. A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design
33. A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC
34. 自動設計に適したレイアウト・ドリブンによるミックストシグナルLSI設計手法のGHz PLL等への適用拡大
35. Charge-Domain Time-to-Digital Converter and Its Application to Fractional-N Frequency Synthesizer
36. A 0.5-to-1 V 9-Bit 15-to-90 Ms/S Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier
37. A Varactor-Less and Dither-Less LC-Digitally Controlled Oscillator with 9-bit Fine Bank, 0.26 mm2 Area, and 6.7 kHz Frequency Resolution
38. A 0.8 ps-LSB, 10-bit, 0.018 mm2 Time-to-Digital Converter
39. A 2 GHz 3.1 mW type-I digital ring-based PLL
40. A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC
41. Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell
42. A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise
43. 積分器とSARADCを用いた1ps分解能の時間・デジタル変換器
44. Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC
45. A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier
46. Picosecond Resolution Time-to-Digital Converter Using ${{\rm G}_{\rm m}} \hbox{-C}$ Integrator and SAR-ADC
47. A 1ps-Resolution Integrator-Based Time-to-Digital Converter Using a SAR-ADC in 90nm CMOS
48. A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC
49. A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS
50. Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers
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